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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 msp430fr599x, msp430fr596x mixed-signal microcontrollers 1 device overview 1 1.1 features 1 (1) minimum supply voltage is restricted by svs levels. (2) the rtc is clocked by a 3.7-pf crystal. ? embedded microcontroller ? 16-bit risc architecture up to 16 ? mhz clock ? up to 256kb of ferroelectric random access memory (fram) ? ultra-low-power writes ? fast write at 125 ns per word (64kb in 4 ms) ? flexible allocation of data and application code in memory ? 10 15 write cycle endurance ? radiation resistant and nonmagnetic ? wide supply voltage range: 1.8 v to 3.6 v (1) ? optimized ultra-low-power modes ? active mode: 118 a/mhz ? standby with vlo (lpm3): 500 na ? standby with real-time clock (rtc) (lpm3.5): 350 na (2) ? shutdown (lpm4.5): 45 na ? low-energy accelerator (lea) for signal processing (msp430fr599x only) ? operation independent of cpu ? 4kb of ram shared with cpu ? efficient 256-point complex fft: up to 40x faster than arm ? cortex ? -m0+ core ? intelligent digital peripherals ? 32-bit hardware multiplier (mpy) ? 6-channel internal dma ? rtc with calendar and alarm functions ? six 16-bit timers with up to seven capture/compare registers each ? 32- and 16-bit cyclic redundancy check (crc) ? high-performance analog ? 16-channel analog comparator ? 12-bit analog-to-digital converter (adc) featuring window comparator, internal reference and sample-and-hold, up to 20 external input channels ? multifunction input/output ports ? all pins support capacitive-touch capability with no need for external components ? accessible bit-, byte-, and word-wise (in pairs) ? edge-selectable wake from lpm on all ports ? programmable pullup and pulldown on all ports ? code security and encryption ? 128- or 256-bit aes security encryption and decryption coprocessor ? random number seed for random number generation algorithms ? ip encapsulation protects memory from external access ? enhanced serial communication ? up to four eusci_a serial communication ports ? uart with automatic baud-rate detection ? irda encode and decode ? up to four eusci_b serial communication ports ? i 2 c with multiple-slave addressing ? hardware uart or i 2 c bootloader (bsl) ? flexible clock system ? fixed-frequency dco with 10 selectable factory-trimmed frequencies ? low-power low-frequency internal clock source (vlo) ? 32-khz crystals (lfxt) ? high-frequency crystals (hfxt) ? development tools and software (also see section 8.3 ) ? development kits ( msp-exp430fr5994 launchpad ? development kit and msp ? ts430pn80b target socket board) ? msp430ware ? software for msp430 ? microcontrollers ? section 3 summarizes the available device variants and package options ? for complete module descriptions, see the msp430fr58xx, msp430fr59xx, msp430fr68xx, and msp430fr69xx family user ' s guide productfolder ordernow technical documents tools & software support &community referencedesign
2 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 device overview copyright ? 2016 ? 2017, texas instruments incorporated 1.2 applications ? grid infrastructure ? factory automation and control ? building automation ? portable health and fitness ? wearable electronics 1.3 description the msp430f599x microcontrollers (mcus) take low power and performance to the next level with the unique low-energy accelerator (lea) for digital signal processing. this accelerator delivers 40x the performance of arm ? cortex ? -m0+ mcus to help developers efficiently process data using complex functions such as fft, fir, and matrix multiplication. implementation requires no dsp expertise with a free optimized dsp library available. additionally, with up to 256kb of unified memory with fram, these devices offer more space for advanced applications and flexibility for effortless implementation of over-the- air firmware updates. the msp ultra-low-power (ulp) fram microcontroller platform combines uniquely embedded fram and a holistic ultra-low-power system architecture, allowing system designers to increase performance while lowering energy consumption. fram technology combines the low-energy fast writes, flexibility, and endurance of ram with the nonvolatile behavior of flash. msp430fr599x mcus are supported by an extensive hardware and software ecosystem with reference designs and code examples to get your design started quickly. development kits for the msp430fr599x include the msp-exp430fr5994 launchpad ? development kit and the msp-ts430pn80b 80-pin target development board . ti also provides free msp430ware ? software , which is available as a component of code composer studio ? ide desktop and cloud versions within ti resource explorer. (1) for the most current part, package, and ordering information for all available devices, see the package option addendum in section 9 , or see the ti website at www.ti.com . (2) for a comparison of all available device variants, see section 3 . (3) the sizes shown here are approximations. for the package dimensions with tolerances, see the mechanical data in section 9 . device information (1) (2) part number package body size (3) msp430fr5994izvw nfbga (87) 6 mm 6 mm msp430fr5994ipn lqfp (80) 12 mm 12 mm msp430fr5994ipm lqfp (64) 10 mm 10 mm msp430fr5994irgz vqfn (48) 7 mm 7 mm
3 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 device overview copyright ? 2016 ? 2017, texas instruments incorporated 1.4 functional block diagram figure 1-1 shows the functional block diagram of the devices. a. the device has 8kb of ram, and 4kb of the ram is shared with the lea subsystem. the cpu has priority over the lea subsystem. b. the lea subsystem is available on the msp430fr599x mcus only. figure 1-1. functional block diagram eem (s: 3+1) comp_e (up to 16 inputs) frctl_a 256kb128kb ram 4kb + 4kb power mgmt ldo svs brownout smclk aclk lfxout, hfxout lfxin, hfxin spy-bi-wire bus control logic mabmdb mab mdb mclk p1.x, p2.x 2x8 i/o port pj 1x8 i/os i/o ports p3 4 2x8 i/os pb 1x16 i/os , p i/o ports p1, p2 2x8 i/os pa 1x16 i/os p3.x, p4.x pj.x 1x 2x8 8 mpy32 aes256 security en decryption (128, 256) cryption, adc12_b (up to 16 standard inputs, up to 8 differential inputs) clock system cpuxv2 incl. 16 registers jtag interface dma controller 6 channel watchdog ref_a voltage reference mpu ip encap t 0 timer_b 7 cc registers (int, ext) b ta0 timer_a 3 cc registers (int, ext) ta1 timer_a 3 cc registers (int, ext) t 2(int) t 3(int) timer_a 2 cc registers aa rtc_c eusci_b0 (i2c, spi) eusci_b1eusci_b2 eusci_b3 capacitive touch i/o 0, capacitive touch i/o 1 lpm3.5 domain lea subsystem eusci_a0eusci_a1 (uart, irda, spi) eusci_a2eusci_a3 i/o ports p7 2x8 i/os pd 1x16 i/os , p8 i/o ports p5, p6 2x8 i/os pc 1x16 i/os p5.x, p6.x p7.x, p8.x 2x8 2x8 crc32 crc-32- iso-3309 crc16 crc-16- ccitt ta4 timer_a 2 cc registers (int, ext) tiny ram 22b copyright ? 2016, texas instruments incorporated
4 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 revision history copyright ? 2016 ? 2017, texas instruments incorporated table of contents 1 device overview ......................................... 1 1.1 features .............................................. 1 1.2 applications ........................................... 2 1.3 description ............................................ 2 1.4 functional block diagram ............................ 3 2 revision history ......................................... 4 3 device comparison ..................................... 5 3.1 related products ..................................... 6 4 terminal configuration and functions .............. 7 4.1 pin diagrams ......................................... 7 4.2 pin attributes ........................................ 12 4.3 signal descriptions .................................. 18 4.4 pin multiplexing ..................................... 25 4.5 buffer types ......................................... 25 4.6 connection of unused pins ......................... 25 5 specifications ........................................... 26 5.1 absolute maximum ratings ......................... 26 5.2 esd ratings ........................................ 26 5.3 recommended operating conditions ............... 27 5.4 active mode supply current into v cc excluding external current ..................................... 28 5.5 typical characteristics, active mode supply currents ............................................. 29 5.6 low-power mode (lpm0, lpm1) supply currents into v cc excluding external current ................ 29 5.7 low-power mode (lpm2, lpm3, lpm4) supply currents (into v cc ) excluding external current .... 30 5.8 low-power mode (lpmx.5) supply currents (into v cc ) excluding external current .................... 32 5.9 typical characteristics, low-power mode supply currents ............................................. 33 5.10 typical characteristics, current consumption per module .............................................. 34 5.11 thermal packaging characteristics ................ 34 5.12 timing and switching characteristics ............... 35 6 detailed description ................................... 64 6.1 overview ............................................ 64 6.2 cpu ................................................. 64 6.3 low-energy accelerator (lea) for signal processing (msp430fr599x only) ................. 64 6.4 operating modes .................................... 65 6.5 interrupt vector table and signatures .............. 67 6.6 bootloader (bsl) .................................... 70 6.7 jtag operation ..................................... 71 6.8 fram controller a (frctl_a) ..................... 72 6.9 ram ................................................ 72 6.10 tiny ram ............................................ 72 6.11 memory protection unit (mpu) including ip encapsulation ....................................... 72 6.12 peripherals .......................................... 73 6.13 input/output diagrams .............................. 84 6.14 device descriptors (tlv) .......................... 122 6.15 memory map ....................................... 125 6.16 identification ........................................ 143 7 applications, implementation, and layout ...... 144 7.1 device connection and layout fundamentals .... 144 7.2 peripheral- and interface-specific design information ......................................... 148 8 device and documentation support .............. 150 8.1 getting started and next steps ................... 150 8.2 device nomenclature .............................. 150 8.3 tools and software ................................ 152 8.4 documentation support ............................ 154 8.5 related links ...................................... 155 8.6 community resources ............................. 155 8.7 trademarks ........................................ 155 8.8 electrostatic discharge caution ................... 155 8.9 export control notice .............................. 155 8.10 glossary ............................................ 155 9 mechanical, packaging, and orderable information ............................................. 156 2 revision history changes from october 18, 2016 to january 31, 2017 page ? changed document status from advance information to production data .................................................... 1 ? updated all electrical and timing specifications and typical characteristics graphs with production data ............... 26
copyright ? 2016 ? 2017, texas instruments incorporated device comparison submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 5 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 3 device comparison table 3-1 summarizes the available family members. (1) for the most current package and ordering information, see the package option addendum in section 9 , or see the ti website at www.ti.com . (2) package drawings, standard packing quantities, thermal data, symbolization, and pcb design guidelines are available at www.ti.com/packaging . (3) each number in the sequence represents an instantiation of timer_a with its associated number of capture/compare registers and pwm output generators available. for example, a number sequence of 3, 5 would represent two instantiations of timer_a, the first instantiation having 3 capture/compare registers and pwm output generators and the second instantiation having 5 capture/compare registers and pwm output generators, respectively. (4) each number in the sequence represents an instantiation of timer_b with its associated number of capture/compare registers and pwm output generators available. for example, a number sequence of 3, 5 would represent two instantiations of timer_b, the first instantiation having 3 capture/compare registers and pwm output generators and the second instantiation having 5 capture/compare registers and pwm output generators, respectively. (5) eusci_a supports uart with automatic baud-rate detection, irda encode and decode, and spi. (6) eusci_b supports i 2 c with multiple slave addresses and spi. (7) timers ta0 and ta1 provide internal and external capture/compare inputs and internal and external pwm outputs. (8) timers ta2 and ta3 provide only internal capture/compare inputs and only internal pwm outputs (if any), whereas timer ta4 provides internal and external capture/compare inputs and internal and external pwm outputs (note: ta4 in the rgz package provide only internal capture/compare inputs and only internal pwm outputs.). table 3-1. device comparison (1) (2) device fram (kb) sram (kb) clock system lea adc12_b comp_e timer_a (3) timer_b (4) eusci aes bsl i/os package a (5) b (6) msp430fr5994 256 8 dco hfxt lfxt yes 20 ext, 2 int ch. 16 ch. 3, 3 (7) 2, 2,2 (8) 7 4 4 yes uart 68 80 pn (lqfp) 87 zvw (nfbga) 17 ext, 2 int ch. 3 3 54 64 pm (lqfp) 16 ext, 2 int ch. 2 1 40 48 rgz (vqfn) msp430fr5992 128 8 dco hfxt lfxt yes 20 ext, 2 int ch. 16 ch. 3, 3 (7) 2, 2,2 (8) 7 4 4 yes uart 68 80 pn (lqfp) 87 zvw (nfbga) 17 ext, 2 int ch. 3 3 54 64 pm (lqfp) 16 ext, 2 int ch. 2 1 40 48 rgz (vqfn) msp430fr5964 256 8 dco hfxt lfxt no 20 ext, 2 int ch. 16 ch. 3, 3 (7) 2, 2,2 (8) 7 4 4 yes uart 68 80 pn (lqfp) 87 zvw (nfbga) 17 ext, 2 int ch. 3 3 54 64 pm (lqfp) 16 ext, 2 int ch. 2 1 40 48 rgz (vqfn) msp430fr5962 128 8 dco hfxt lfxt no 20 ext, 2 int ch. 16 ch. 3, 3 (7) 2, 2,2 (8) 7 4 4 yes uart 68 80 pn (lqfp) 87 zvw (nfbga) 17 ext, 2 int ch. 3 3 54 64 pm (lqfp) 16 ext, 2 int ch. 2 1 40 48 rgz (vqfn) msp430fr59941 256 8 dco hfxt lfxt yes 20 ext, 2 int ch. 16 ch. 3, 3 (7) 2, 2,2 (8) 7 4 4 yes i 2 c 68 80 pn (lqfp) 87 zvw (nfbga) 17 ext, 2 int ch. 3 3 54 64 pm (lqfp) 16 ext, 2 int ch. 2 1 40 48 rgz (vqfn)
6 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 device comparison copyright ? 2016 ? 2017, texas instruments incorporated 3.1 related products for information about other devices in this family of products or related products, see the following links. products for ti microcontrollers ti's low-power and high-performance mcus, with wired and wireless connectivity options, are optimized for a broad range of applications. products for msp430 ultra-low-power microcontrollers one platform. one ecosystem. endless possibilities. enabling the connected world with innovations in ultra-low-power microcontrollers with advanced peripherals for precise sensing and measurement. msp430frxx fram microcontrollers 16-bit microcontrollers for ultra-low-power sensing and system management in building automation, smart grid, and industrial designs. companion products for msp430fr5994 review products that are frequently purchased or used with this product. reference designs for msp430fr5994 the ti designs reference design library is a robust reference design library that spans analog, embedded processor, and connectivity. created by ti experts to help you jump start your system design, all ti designs include schematic or block diagrams, boms, and design files to speed your time to market. search and download designs at ti.com/tidesigns .
7 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 terminal configuration and functions copyright ? 2016 ? 2017, texas instruments incorporated 4 terminal configuration and functions 4.1 pin diagrams figure 4-1 shows the bottom view of the pinout of the 87-pin zvw package, and figure 4-2 shows the top view of the pinout. note: on devices with uart bsl: p2.0 is bsltx, p2.1 is bslrx note: on devices with i 2 c bsl: p1.6 is bslsda, p1.7 is bslscl figure 4-1. 87-pin zvw package (bottom view) dvss3 rst dvcc3 p2.3 dgnd l1 l2 l3 l4 l5 l6 l7 l8 l9 l10 l11 k1 j1 h1 g1 f1 e1 d1 c1 b1 a1 b1 k2 k3 k4 k5 k6 k7 k8 k9 k10 k11 j2 h2 g2 f2 e2 d2c2 a2 b3a3 h4 g4 f4 e4 d4 b4a4 h5d5 b5a5 h6d6 b6a6 h7d7 b7a7 h8 g8 f8 e8 d8 b8a8 b9a9 j10 h10 g10 f10 e10 d10c10 b10a10 j11 h11 g11 f11 e11 d11 c11 b11 a11 agnd dgnd p8.2 p3.4 avss1 p2.0 lfout lfin p2.7 hfout hfin dvss1 p2.4 p2.2 p1.7 p5.1 p5.2 p4.6 dgnd p5.4 p2.6 tst p8.3 p3.6 p3.7 p4.4 p4.5 p5.5 p4.2 p4.3 p2.5 p5.7 p5.6 p4.0 p7.7 p4.1 p6.4 p6.5 p7.4 p7.5 p7.6 p6.6 avss3 p7.2 pj.3 p7.3 p6.0 avss2 p8.0 p4.7 p6.1 pj.1 pj.2 p6.7 pj.0 p1.5 p7.1 p1.4 p6.3 p3.2 p3.1 p1.2 agnd dgnd p1.3 p7.0 dvcc2 p6.2 p3.3 p3.0 p1.1 p1.0 dvss2 avcc1 dvcc1 dgnd p2.1 p8.1 p3.5 p1.6 p5.0 p5.3
8 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 terminal configuration and functions copyright ? 2016 ? 2017, texas instruments incorporated figure 4-2. 87-pin zvw package (top view) l1 l2 l3 l4 l5 l6 l7 l8 l9 l10 l11 k1 j1 h1 g1 f1 e1 d1c1 b1a1 l1 k2 k3 k4 k5 k6 k7 k8 k9 k10 k11 j2 h2 g2 f2 e2 d2c2 a2 b3a3 h4 g4 f4 e4 d4 b4a4 h5d5 b5a5 h6d6 b6a6 h7d7 b7a7 h8 g8 f8 e8 d8 b8a8 b9a9 j10 h10 g10 f10 e10 d10c10 b10a10 j11 h11 g11 f11 e11 d11 c11 b11 a11 dvss3 rst dvcc3 p2.3 dgnd agnd dgnd p8.2 p3.4 avss1 p2.0 lfout lfin p2.7 hfout hfin dvss1 p2.4 p2.2 p1.7 p5.1 p5.2 p4.6 dgnd p5.4 p2.6 tst p8.3 p3.6 p3.7 p4.4 p4.5 p5.5 p4.2 p4.3 p2.5 p5.7 p5.6 p4.0 p7.7 p4.1 p6.4 p6.5 p7.4 p7.5 p7.6 p6.6 avss3 p7.2 pj.3 p7.3 p6.0 avss2 p8.0 p4.7 p6.1 pj.1 pj.2 p6.7 pj.0 p1.5 p7.1 p1.4 p6.3 p3.2 p3.1 p1.2 agnd dgnd p1.3 p7.0 dvcc2 p6.2 p3.3 p3.0 p1.1 p1.0 dvss2 avcc1 dvcc1 dgnd p2.1 p8.1 p3.5 p1.6 p5.0 p5.3
9 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 terminal configuration and functions copyright ? 2016 ? 2017, texas instruments incorporated figure 4-3 shows the pinout of the 80-pin pn package. note: on devices with uart bsl: p2.0 is bsltx, p2.1 is bslrx note: on devices with i 2 c bsl: p1.6 is bslsda, p1.7 is bslscl figure 4-3. 80-pin pn package (top view) 12 3 4 5 6 7 8 9 10 11 1213 14 15 16 17 18 19 20 21 dvss3 22 dvcc2 23 24 25 26 27 28 29 30 31 32 33 34 p5.0/ucb1simo/ucb1sda 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 dvcc1 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 p1.4/tb0.1/uca0ste/a4/c4 p1.0/ta0.1/dmae0/rtcclk/a0/c0/vref-/veref- p1.1/ta0.2/ta1clk/cout/a1/c1/vref+/veref+ p1.2/ta1.1/ta0clk/cout/a2/c2 p3.0/a12/c12p3.1/a13/c13 p3.2/a14/c14 p3.3/a15/c15 p1.3/ta1.2/ucb0ste/a3/c3 p1.5/tb0.2/uca0clk/a5/c5 p4.7 pj.0/tdo/tb0outh/smclk/srscg1/c6 pj.1/tdi/tclk/mclk/srscg0/c7 pj.2/tms/aclk/sroscoff/c8 pj.3/tck/srcpuoff/c9 p4.0/a8 p4.1/a9 p4.2/a10 p4.3/a11 p2.5/tb0.0/uca1txd/uca1simo p2.6/tb0.1/uca1rxd/uca1somi test/sbwtck rst/nmi/sbwtdio p2.0/tb0.6/uca0txd/uca0simo/tb0clk/aclk p2.1/tb0.0/uca0rxd/uca0somi p2.2/tb0.2/ucb0clk p3.4/tb0.3/smclk p3.5/tb0.4/cout p3.6/tb0.5 p3.7/tb0.6 p1.6/tb0.3/ucb0simo/ucb0sda/ta0.0 p1.7/tb0.4/ucb0somi/ucb0scl/ta1.0 p4.4/tb0.5 p4.5 p4.6 dvss1 p2.7 p2.3/ta0.0/uca1ste/a6/c10 avss3 pj.6/hfxin pj.7/hfxout avss2 pj.4/lfxin pj.5/lfxout avss1 avcc1 p2.4/ta1.0/uca1clk/a7/c11 dvss2 p5.1/ucb1somi/ucb1scl p5.2/ucb1clk/ta4clk p5.3/ucb1ste p5.4/uca2txd/uca2simo/tb0outh p5.5/uca2rxd/uca2somi/aclk p5.6/uca2clk/ta4.0/smclk p5.7/uca2ste/ta4.1/mclk p8.0 p6.0/uca3txd/uca3simo p6.1/uca3rxd/uca3somi p6.2/uca3clk p6.3/uca3ste p8.1 dvcc3 p6.4/ucb3simo/ucb3sda p6.5/ucb3somi/ucb3scl p6.6/ucb3clk p6.7/ucb3ste p8.2 p8.3 p7.0/ucb2simo/ucb2sda p7.2/ucb2clk p7.3/ucb2ste/ta4.1 p7.1/ucb2somi/ucb2scl p7.4//ta4.0/a16 p7.6/a18p7.7/a19 p7.5/a17
10 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 terminal configuration and functions copyright ? 2016 ? 2017, texas instruments incorporated figure 4-4 shows the pinout of the 64-pin pm package. note: on devices with uart bsl: p2.0 is bsltx, p2.1 is bslrx note: on devices with i 2 c bsl: p1.6 is bslsda, p1.7 is bslscl figure 4-4. 64-pin pm package (top view) 12 3 4 5 6 7 8 9 10 11 1213 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 dvcc2 p1.4/tb0.1/uca0ste/a4/c4 p1.0/ta0.1/dmae0/rtcclk/a0/c0/vref-/veref- p1.1/ta0.2/ta1clk/cout/a1/c1/vref+/veref+ p1.2/ta1.1/ta0clk/cout/a2/c2 p3.0/a12/c12 p3.1/a13/c13 p3.2/a14/c14 p3.3/a15/c15 p1.3/ta1.2/ucb0ste/a3/c3 p1.5/tb0.2/uca0clk/a5/c5 p4.7 dvss2 p8.0 p7.0/ucb2simo/ucb2sda p7.1/ucb2somi/ucb2scl pj.0/tdo/tb0outh/smclk/srscg1/c6 pj.1/tdi/tclk/mclk/srscg0/c7 pj.2/tms/aclk/sroscoff/c8 pj.3/tck/srcpuoff/c9 p4.0/a8 p4.1/a9 p4.2/a10 p4.3/a11 p2.5/tb0.0/uca1txd/uca1simo p2.6/tb0.1/uca1rxd/uca1somi test/sbwtck rst/nmi/sbwtdio p2.0/tb0.6/uca0txd/uca0simo/tb0clk/aclk p7.2/ucb2clk p7.3/ucb2ste/ta4.1 p7.4//ta4.0/a16 p5.0/ucb1simo/ucb1sda p2.1/tb0.0/uca0rxd/uca0somi p2.2/tb0.2/ucb0clk p3.4/tb0.3/smclk p3.5/tb0.4/cout p3.6/tb0.5 p3.7/tb0.6 p1.6/tb0.3/ucb0simo/ucb0sda/ta0.0 p1.7/tb0.4/ucb0somi/ucb0scl/ta1.0 p4.4/tb0.5 p4.5 p4.6 dvss1 p5.1/ucb1somi/ucb1scl p5.2/ucb1clk/ta4clk p5.3/ucb1ste dvcc1 p2.7 p2.3/ta0.0/uca1ste/a6/c10 avss3 pj.6/hfxin pj.7/hfxout avss2 pj.4/lfxin pj.5/lfxout avss1 avcc1 p2.4/ta1.0/uca1clk/a7/c11 p5.4/uca2txd/uca2simo/tb0outh p5.5/uca2rxd/uca2somi/aclk p5.6/uca2clk/ta4.0/smclk p5.7/uca2ste/ta4.1/mclk
11 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 terminal configuration and functions copyright ? 2016 ? 2017, texas instruments incorporated figure 4-5 shows the pinout of the 48-pin rgz package. note: ti recommends connecting the qfn thermal pad to v ss . note: on devices with uart bsl: p2.0 is bsltx, p2.1 is bslrx note: on devices with i 2 c bsl: p1.6 is bslsda, p1.7 is bslscl figure 4-5. 48-pin rgz package (top view) p1.4/tb0.1/uca0ste/a4/c4 1 p1.0/ta0.1/dmae0/rtcclk/a0/c0/vref-/veref- 2 p1.1/ta0.2/ta1clk/cout/a1/c1/vref+/veref+ 3 p1.2/ta1.1/ta0clk/cout/a2/c2 4 p3.0/a12/c12 5 p3.1/a13/c13 6 p3.2/a14/c14 7 p3.3/a15/c15 8 p1.3/ta1.2/ucb0ste/a3/c3 9 10 p1.5/tb0.2/uca0clk/a5/c5 11 p4.7 12 pj.0/tdo/tb0outh/smclk/srscg1/c6 13 pj.1/tdi/tclk/mclk/srscg0/c7 14 pj.2/tms/aclk/sroscoff/c8 15 pj.3/tck/srcpuoff/c9 16 p4.0/a8 17 p4.1/a9 18 p4.2/a10 19 p4.3/a11 20 p2.5/tb0.0/uca1txd/uca1simo 21 p2.6/tb0.1/uca1rxd/uca1somi 22 test/sbwtck 23 rst/nmi/sbwtdio 24 p2.0/tb0.6/uca0txd/uca0simo/tb0clk/aclk 25 p2.1/tb0.0/uca0rxd/uca0somi 26 p2.2/tb0.2/ucb0clk 27 p3.4/tb0.3/smclk 28 p3.5/tb0.4/cout 29 p3.6/tb0.5 30 p3.7/tb0.6 31 p1.6/tb0.3/ucb0simo/ucb0sda/ta0.0 32 p1.7/tb0.4/ucb0somi/ucb0scl/ta1.0 33 p4.4/tb0.5 34 p4.5 35 p4.6 36 dvss1 37 dvcc1 38 p2.7 39 p2.3/ta0.0/uca1ste/a6/c10 40 41 avss 42 pj.6/hfxin 43 pj.7/hfxout 44 avss 45 pj.4/lfxin 46 pj.5/lfxout 47 avss1 48 avcc1 p2.4/ta1.0/uca1clk/a7/c11
12 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 terminal configuration and functions copyright ? 2016 ? 2017, texas instruments incorporated (1) n/a = not available (2) the signal that is listed first for each pin is the reset default pin name. (3) to determine the pin mux encodings for each pin, see section 6.13 . (4) signal types: i = input, o = output, i/o = input or output. (5) buffer types: lvcmos, analog, or power (see table 4-3 for details) (6) the power source shown in this table is the i/o power source, which may differ from the module power source. (7) reset states: off = high impedance with schmitt-trigger input and pullup or pulldown (if available) disabled n/a = not applicable 4.2 pin attributes table 4-1 summarizes the attributes of the pins. table 4-1. pin attributes pin number (1) signal name (2) (3) signal type (4) buffer type (5) power source (6) reset state after bor (7) pn pm rgz zvw 1 1 1 a10 p1.0 i/o lvcmos dvcc off ta0.1 i/o lvcmos dvcc ? dmae0 i lvcmos dvcc ? rtcclk o lvcmos dvcc ? a0 i analog dvcc ? c0 i analog dvcc ? vref- o analog dvcc ? veref- i analog dvcc ? 2 2 2 a9 p1.1 i/o lvcmos dvcc off ta0.2 i/o lvcmos dvcc ? ta1clk i lvcmos dvcc ? cout o lvcmos dvcc ? a1 i analog dvcc ? c1 i analog dvcc ? vref+ o analog dvcc ? veref+ i analog dvcc ? 3 3 3 b9 p1.2 i/o lvcmos dvcc off ta1.1 i/o lvcmos dvcc ? ta0clk i lvcmos dvcc ? cout o lvcmos dvcc ? a2 i analog dvcc ? c2 i analog dvcc ? 4 4 4 a8 p3.0 i/o lvcmos dvcc off a12 i analog dvcc ? c12 i analog dvcc ? 5 5 5 b8 p3.1 i/o lvcmos dvcc ? a13 i analog dvcc ? c13 i analog dvcc ? 6 6 6 b7 p3.2 i/o lvcmos dvcc off a14 i analog dvcc ? c14 i analog dvcc ? 7 7 7 a7 p3.3 i/o lvcmos dvcc off a15 i analog dvcc ? c15 i analog dvcc ? 8 ? ? d8 p6.0 i/o lvcmos dvcc off uca3txd o lvcmos dvcc ? uca3simo i/o lvcmos dvcc ?
13 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 terminal configuration and functions copyright ? 2016 ? 2017, texas instruments incorporated table 4-1. pin attributes (continued) pin number (1) signal name (2) (3) signal type (4) buffer type (5) power source (6) reset state after bor (7) pn pm rgz zvw 9 ? ? d7 p6.1 i/o lvcmos dvcc off uca3rxd i lvcmos dvcc ? uca3somi i/o lvcmos dvcc ? 10 ? ? a6 p6.2 i/o lvcmos dvcc off uca3clk i/o lvcmos dvcc ? 11 ? ? b6 p6.3 i/o lvcmos dvcc off uca3ste i/o lvcmos dvcc ? 12 8 8 d6 p4.7 i/o lvcmos dvcc off 13 9 ? a5 p7.0 i/o lvcmos dvcc off ucb2simo i/o lvcmos dvcc ? ucb2sda i/o lvcmos dvcc ? 14 10 ? b5 p7.1 i/o lvcmos dvcc off ucb2somi i/o lvcmos dvcc ? ucb2scl i/o lvcmos dvcc ? 15 11 ? d5 p8.0 i/o lvcmos dvcc off 16 12 9 a4 p1.3 i/o lvcmos dvcc off ta1.2 i/o lvcmos dvcc ? ucb0ste i/o lvcmos dvcc ? a3 i analog dvcc ? c3 i analog dvcc ? 17 13 10 b3 p1.4 i/o lvcmos dvcc off tb0.1 i/o lvcmos dvcc ? uca0ste i/o lvcmos dvcc ? a4 i analog dvcc ? c4 i analog dvcc ? 18 14 11 b4 p1.5 i/o lvcmos dvcc off tb0.2 i/o lvcmos dvcc ? uca0clk i/o lvcmos dvcc ? a5 i analog dvcc ? c5 i analog dvcc ? 19 15 ? a2 dvss2 p power ? n/a 20 16 ? a3 dvcc2 p power ? n/a 21 17 12 b1 pj.0 i/o lvcmos dvcc off tdo o lvcmos dvcc ? tb0outh i lvcmos dvcc ? smclk o lvcmos dvcc ? srscg1 o lvcmos dvcc ? c6 i analog dvcc ? 22 18 13 c1 pj.1 i/o lvcmos dvcc off tdi i lvcmos dvcc ? tclk i lvcmos dvcc ? mclk o lvcmos dvcc ? srscg0 o lvcmos dvcc ? c7 i analog dvcc ?
14 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 terminal configuration and functions copyright ? 2016 ? 2017, texas instruments incorporated table 4-1. pin attributes (continued) pin number (1) signal name (2) (3) signal type (4) buffer type (5) power source (6) reset state after bor (7) pn pm rgz zvw 23 19 14 c2 pj.2 i/o lvcmos dvcc off tms i lvcmos dvcc ? aclk o lvcmos dvcc ? sroscoff o lvcmos dvcc ? c8 i analog dvcc ? 24 20 15 d2 pj.3 i/o lvcmos dvcc off tck i lvcmos dvcc ? srcpuoff o lvcmos dvcc ? c9 i analog dvcc ? 25 21 ? d1 p7.2 i/o lvcmos dvcc off ucb2clk i/o lvcmos dvcc ? 26 22 ? d4 p7.3 i/o lvcmos dvcc off ucb2ste i/o lvcmos dvcc ? ta4.1 i/o lvcmos dvcc ? 27 23 ? e1 p7.4 i/o lvcmos dvcc off ta4.0 i/o lvcmos dvcc ? a16 i analog dvcc ? 28 ? ? e2 p7.5 i/o lvcmos dvcc off a17 i analog dvcc ? 29 ? ? e4 p7.6 i/o lvcmos dvcc off a18 i analog dvcc ? 30 ? ? f2 p7.7 i/o lvcmos dvcc off a19 i analog dvcc ? 31 24 16 f1 p4.0 i/o lvcmos dvcc off a8 i analog dvcc ? 32 25 17 f4 p4.1 i/o lvcmos dvcc off a9 i analog dvcc ? 33 26 18 g1 p4.2 i/o lvcmos dvcc off a10 i analog dvcc ? 34 27 19 g2 p4.3 i/o lvcmos dvcc off a11 i analog dvcc ? 35 28 20 g4 p2.5 i/o lvcmos dvcc off tb0.0 i/o lvcmos dvcc ? uca1txd o lvcmos dvcc ? uca1simo i/o lvcmos dvcc ? 36 29 21 h1 p2.6 i/o lvcmos dvcc off tb0.1 o lvcmos dvcc ? uca1rxd i lvcmos dvcc ? uca1somi i/o lvcmos dvcc ? 37 30 22 h2 test i lvcmos dvcc off sbwtck i lvcmos dvcc ? 38 31 23 j2 rst i lvcmos dvcc off nmi i lvcmos dvcc ? sbwtdio i/o lvcmos dvcc ? 39 ? ? j1 dvss3 p power ? n/a 40 ? ? k1 dvcc3 p power ? n/a
15 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 terminal configuration and functions copyright ? 2016 ? 2017, texas instruments incorporated table 4-1. pin attributes (continued) pin number (1) signal name (2) (3) signal type (4) buffer type (5) power source (6) reset state after bor (7) pn pm rgz zvw 41 32 24 l2 p2.0 i/o lvcmos dvcc off tb0.6 i/o lvcmos dvcc ? uca0txd o lvcmos dvcc ? bsltx o lvcmos dvcc ? uca0simo i/o lvcmos dvcc ? tb0clk i lvcmos dvcc ? aclk o lvcmos dvcc ? 42 33 25 l3 p2.1 i/o lvcmos dvcc off tb0.0 i/o lvcmos dvcc ? uca0rxd i lvcmos dvcc ? bslrx i lvcmos dvcc ? uca0somi i/o lvcmos dvcc ? 43 34 26 k3 p2.2 i/o lvcmos dvcc off tb0.2 o lvcmos dvcc ? ucb0clk i/o lvcmos dvcc ? 44 ? ? l4 p8.1 i/o lvcmos dvcc off 45 ? ? k4 p8.2 i/o lvcmos dvcc off 46 ? ? h4 p8.3 i/o lvcmos dvcc off 47 35 27 k5 p3.4 i/o lvcmos dvcc off tb0.3 i/o lvcmos dvcc ? smclk o lvcmos dvcc ? 48 36 28 l5 p3.5 i/o lvcmos dvcc off tb0.4 i/o lvcmos dvcc ? cout o lvcmos dvcc ? 49 37 29 h5 p3.6 i/o lvcmos dvcc off tb0.5 i/o lvcmos dvcc ? 50 38 30 h6 p3.7 i/o lvcmos dvcc off tb0.6 i/o lvcmos dvcc ? 51 39 31 l6 p1.6 i/o lvcmos dvcc off tb0.3 i/o lvcmos dvcc ? ucb0simo i/o lvcmos dvcc ? ucb0sda i/o lvcmos dvcc ? bslsda i/o lvcmos dvcc ? ta0.0 i/o lvcmos dvcc ? 52 40 32 k6 p1.7 i/o lvcmos dvcc off tb0.4 i/o lvcmos dvcc ? ucb0somi i/o lvcmos dvcc ? ucb0scl i/o lvcmos dvcc ? bslscl i/o lvcmos dvcc ? ta1.0 i/o lvcmos dvcc ? 53 41 ? l7 p5.0 i/o lvcmos dvcc off ucb1simo i/o lvcmos dvcc ? ucb1sda i/o lvcmos dvcc ? 54 42 ? k7 p5.1 i/o lvcmos dvcc off ucb1somi i/o lvcmos dvcc ? ucb1scl i/o lvcmos dvcc ?
16 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 terminal configuration and functions copyright ? 2016 ? 2017, texas instruments incorporated table 4-1. pin attributes (continued) pin number (1) signal name (2) (3) signal type (4) buffer type (5) power source (6) reset state after bor (7) pn pm rgz zvw 55 43 ? k8 p5.2 i/o lvcmos dvcc off ucb1clk i/o lvcmos dvcc ? ta4clk i lvcmos dvcc ? 56 44 ? l8 p5.3 i/o lvcmos dvcc off ucb1ste i/o lvcmos dvcc ? 57 45 33 h7 p4.4 i/o lvcmos dvcc off tb0.5 i/o lvcmos dvcc ? 58 46 34 h8 p4.5 i/o lvcmos dvcc off 59 47 35 k9 p4.6 i/o lvcmos dvcc off 60 48 36 l9 dvss1 p power ? n/a 61 49 37 l10 dvcc1 p power ? n/a 62 50 38 f11 p2.7 i/o lvcmos dvcc off 63 51 39 j11 p2.3 i/o lvcmos dvcc off ta0.0 i/o lvcmos dvcc ? uca1ste i/o lvcmos dvcc ? a6 i analog dvcc ? c10 i analog dvcc ? 64 52 40 k11 p2.4 i/o lvcmos dvcc off ta1.0 i/o lvcmos dvcc ? uca1clk i/o lvcmos dvcc ? a7 i analog dvcc ? c11 i analog dvcc ? 65 53 ? j10 p5.4 i/o lvcmos dvcc off uca2txd o lvcmos dvcc ? uca2simo i/o lvcmos dvcc ? tb0outh i lvcmos dvcc ? 66 54 ? h10 p5.5 i/o lvcmos dvcc off uca2rxd i lvcmos dvcc ? uca2somi i/o lvcmos dvcc ? aclk o lvcmos dvcc ? 67 55 ? g10 p5.6 i/o lvcmos dvcc off uca2clk i/o lvcmos dvcc ? ta4.0 i/o lvcmos dvcc ? smclk o lvcmos dvcc ? 68 56 ? g8 p5.7 i/o lvcmos dvcc off uca2ste i/o lvcmos dvcc ? ta4.1 i/o lvcmos dvcc ? mclk o lvcmos dvcc ? 69 ? ? f8 p6.4 i/o lvcmos dvcc off ucb3simo i/o lvcmos dvcc ? ucb3sda i/o lvcmos dvcc ? 70 ? ? f10 p6.5 i/o lvcmos dvcc off ucb3somi i/o lvcmos dvcc ? ucb3scl i/o lvcmos dvcc ? 71 ? ? e8 p6.6 i/o lvcmos dvcc off ucb3clk i/o lvcmos dvcc ?
17 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 terminal configuration and functions copyright ? 2016 ? 2017, texas instruments incorporated table 4-1. pin attributes (continued) pin number (1) signal name (2) (3) signal type (4) buffer type (5) power source (6) reset state after bor (7) pn pm rgz zvw 72 ? ? c10 p6.7 i/o lvcmos dvcc off ucb3ste i/o lvcmos dvcc ? 73 57 41 e10 avss3 p power ? n/a 74 58 42 h11 pj.6 i/o lvcmos dvcc ? hfxin i analog dvcc ? 75 59 43 g11 pj.7 i/o lvcmos dvcc off hfxout o analog dvcc ? 76 60 44 d10 avss2 p power ? n/a 77 61 45 e11 pj.4 i/o lvcmos dvcc off lfxin i analog dvcc ? 78 62 46 d11 pj.5 i/o lvcmos dvcc off lfxout o analog dvcc ? 79 63 47 c11 avss1 p power ? n/a 80 64 48 b11 avcc1 p power ? n/a ? ? ? a1 dgnd p power ? n/a ? ? ? a11 agnd p power ? n/a ? ? ? b10 agnd p power ? n/a ? ? ? k2 dgnd p power ? n/a ? ? ? k10 dgnd p power ? n/a ? ? ? l1 dgnd p power ? n/a ? ? ? l11 dgnd p power ? n/a ? ? pad ? qfn pad p power ? n/a
18 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 terminal configuration and functions copyright ? 2016 ? 2017, texas instruments incorporated (1) n/a = not available (2) i = input, o = output, p = power 4.3 signal descriptions table 4-2 describes the signals for all device variants and package options. table 4-2. signal descriptions function signal name pin no. (1) pin type (2) description zvw pn pm rgz adc a0 a10 1 1 1 i adc analog input a0 a1 a9 2 2 2 i adc analog input a1 a2 b9 3 3 3 i adc analog input a2 a3 a4 16 12 9 i adc analog input a3 a4 b3 17 13 10 i adc analog input a4 a5 b4 18 14 11 i adc analog input a5 a6 j11 63 51 39 i adc analog input a6 a7 k11 64 52 40 i adc analog input a7 a8 f1 31 24 16 i adc analog input a8 a9 f4 32 25 17 i adc analog input a9 a10 g1 33 26 18 i adc analog input a10 a11 g2 34 27 19 i adc analog input a11 a12 a8 4 4 4 i adc analog input a12 a13 b8 5 5 5 i adc analog input a13 a14 b7 6 6 6 i adc analog input a14 a15 a7 7 7 7 i adc analog input a15 a16 e1 27 23 ? i adc analog input a16 a17 e2 28 ? ? i adc analog input a17 a18 e4 29 ? ? i adc analog input a18 a19 f2 30 ? ? i adc analog input a19 vref+ a9 2 2 2 o output of positive reference voltage vref- a10 1 1 1 o output of negative reference voltage veref+ a9 2 2 2 i input for an external positive reference voltage to the adc veref- a10 1 1 1 i input for an external negative reference voltage to the adc bsl (i 2 c) bslscl k6 52 40 32 i/o i 2 c bsl clock bslsda l6 51 39 31 i/o i 2 c bsl data bsl (uart) bslrx l3 42 33 25 i uart bsl receive bsltx l2 41 32 24 o uart bsl transmit clock aclk c2 h10 23 41 66 19 32 54 14 24 o aclk output hfxin h11 74 58 42 i input for high-frequency crystal oscillator hfxt hfxout g11 75 59 43 o output for high-frequency crystal oscillator hfxt lfxin e11 77 61 45 i input for low-frequency crystal oscillator lfxt lfxout d11 78 62 46 o output of low-frequency crystal oscillator lfxt mclk c1 g8 22 68 18 56 13 o mclk output smclk b1 g10 21 47 67 17 35 55 12 27 o smclk output
19 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 terminal configuration and functions copyright ? 2016 ? 2017, texas instruments incorporated table 4-2. signal descriptions (continued) function signal name pin no. (1) pin type (2) description zvw pn pm rgz comparator c0 a10 1 1 1 i comparator input c0 c1 a9 2 2 2 i comparator input c1 c2 b9 3 3 3 i comparator input c2 c3 a4 16 12 9 i comparator input c3 c4 b3 17 13 10 i comparator input c4 c5 b4 18 14 11 i comparator input c5 c6 b1 21 17 12 i comparator input c6 c7 c1 22 18 13 i comparator input c7 c8 c2 23 19 14 i comparator input c8 c9 d2 24 20 15 i comparator input c9 c10 j11 63 51 39 i comparator input c10 c11 k11 64 52 40 i comparator input c11 c12 a8 4 4 4 i comparator input c12 c13 b8 5 5 5 i comparator input c13 c14 b7 6 6 6 i comparator input c14 c15 a7 7 7 7 i comparator input c15 cout a9 b9 2 3 48 2 3 36 2 3 28 o comparator output dma dmae0 a10 1 1 1 i external dma trigger debug sbwtck h2 37 30 22 i spy-bi-wire input clock sbwtdio j2 38 31 23 i/o spy-bi-wire data input/output srcpuoff d2 24 20 15 o low-power debug: cpu status register bit cpuoff sroscoff c2 23 19 14 o low-power debug: cpu status register bit oscoff srscg0 c1 22 18 13 o low-power debug: cpu status register bit scg0 srscg1 b1 21 17 12 o low-power debug: cpu status register bit scg1 tck d2 24 20 15 i test clock tclk c1 22 18 13 i test clock input tdi c1 22 18 13 i test data input tdo b1 21 17 12 o test data output port test h2 37 30 22 i test mode pin ? select digital i/o on jtag pins tms c2 23 19 14 i test mode select gpio p1.0 a10 1 1 1 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p1.1 a9 2 2 2 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p1.2 b9 3 3 3 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p1.3 a4 16 12 9 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p1.4 b3 17 13 10 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p1.5 b4 18 14 11 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p1.6 l6 51 39 31 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p1.7 k6 52 40 32 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5
20 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 terminal configuration and functions copyright ? 2016 ? 2017, texas instruments incorporated table 4-2. signal descriptions (continued) function signal name pin no. (1) pin type (2) description zvw pn pm rgz gpio p2.0 l2 41 32 24 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p2.1 l3 42 33 25 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p2.2 k3 43 34 26 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p2.3 j11 63 51 39 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p2.4 k11 64 52 40 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p2.5 g4 35 28 20 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p2.6 h1 36 29 21 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p2.7 f11 62 50 38 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 gpio p3.0 a8 4 4 4 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p3.1 b8 5 5 5 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p3.2 b7 6 6 6 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p3.3 a7 7 7 7 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p3.4 k5 47 35 27 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p3.5 l5 48 36 28 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p3.6 h5 49 37 29 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p3.7 h6 50 38 30 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 gpio p4.0 f1 31 24 16 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p4.1 f4 32 25 17 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p4.2 g1 33 26 18 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p4.3 g2 34 27 19 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p4.4 h7 57 45 33 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p4.5 h8 58 46 34 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p4.6 k9 59 47 35 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p4.7 d6 12 8 8 i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5
21 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 terminal configuration and functions copyright ? 2016 ? 2017, texas instruments incorporated table 4-2. signal descriptions (continued) function signal name pin no. (1) pin type (2) description zvw pn pm rgz gpio p5.0 l7 53 41 ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p5.1 k7 54 42 ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p5.2 k8 55 43 ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p5.3 l8 56 44 ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p5.4 j10 65 53 ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p5.5 h10 66 54 ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p5.6 g10 67 55 ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p5.7 g8 68 56 ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 gpio p6.0 d8 8 ? ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p6.1 d7 9 ? ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p6.2 a6 10 ? ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p6.3 b6 11 ? ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p6.4 f8 69 ? ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p6.5 f10 70 ? ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p6.6 e8 71 ? ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p6.7 c10 72 ? ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 gpio p7.0 a5 13 9 ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p7.1 b5 14 10 ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p7.2 d1 25 21 ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p7.3 d4 26 22 ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p7.4 e1 27 23 ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p7.5 e2 28 ? ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p7.6 e4 29 ? ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p7.7 f2 30 ? ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5
22 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 terminal configuration and functions copyright ? 2016 ? 2017, texas instruments incorporated table 4-2. signal descriptions (continued) function signal name pin no. (1) pin type (2) description zvw pn pm rgz gpio p8.0 d5 15 11 ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p8.1 l4 44 ? ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p8.2 k4 45 ? ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 p8.3 h4 46 ? ? i/o general-purpose digital i/o with port interrupt and wake up from lpmx.5 gpio pj.0 b1 21 17 12 i/o general-purpose digital i/o pj.1 c1 22 18 13 i/o general-purpose digital i/o pj.2 c2 23 19 14 i/o general-purpose digital i/o pj.3 d2 24 20 15 i/o general-purpose digital i/o pj.4 e11 77 61 45 i/o general-purpose digital i/o pj.5 d11 78 62 46 i/o general-purpose digital i/o pj.6 h11 74 58 42 i/o general-purpose digital i/o pj.7 g11 75 59 43 i/o general-purpose digital i/o i 2 c ucb0scl k6 52 40 32 i/o i 2 c clock ? eusci_b0 i 2 c mode ucb0sda l6 51 39 31 i/o i 2 c data ? eusci_b0 i 2 c mode ucb1scl k7 54 42 ? i/o i 2 c clock ? eusci_b1 i 2 c mode ucb1sda l7 53 41 ? i/o i 2 c data ? eusci_b1 i 2 c mode ucb2scl b5 14 10 ? i/o i 2 c clock ? eusci_b2 i 2 c mode ucb2sda a5 13 9 ? i/o i 2 c data ? eusci_b2 i 2 c mode ucb3scl f10 70 ? ? i/o i 2 c clock ? eusci_b3 i 2 c mode ucb3sda f8 69 ? ? i/o i 2 c data ? eusci_b3 i 2 c mode power agnd b10 a11 ? ? ? p analog ground avcc1 b11 80 64 48 p analog power supply avss1 c11 79 63 47 p analog ground supply avss2 d10 76 60 44 p analog ground supply avss3 e10 73 57 41 p analog ground supply dgnd a1 k2 k10 l1 l11 ? ? ? p digital ground dvcc1 l10 61 49 37 p digital power supply dvcc2 a3 20 16 ? p digital power supply dvcc3 k1 40 ? ? p digital power supply dvss1 l9 60 48 36 p digital ground supply dvss2 a2 19 15 ? p digital ground supply dvss3 j1 39 ? ? p digital ground supply qfn pad ? ? ? pad p qfn package exposed thermal pad. ti recommends connection to v ss . rtc rtcclk a10 1 1 1 o rtc clock calibration output (not available on msp430fr5x5x devices)
23 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 terminal configuration and functions copyright ? 2016 ? 2017, texas instruments incorporated table 4-2. signal descriptions (continued) function signal name pin no. (1) pin type (2) description zvw pn pm rgz spi uca0clk b4 18 14 11 i/o clock signal input ? eusci_a0 spi slave mode clock signal output ? eusci_a0 spi master mode uca0simo l2 41 32 24 i/o slave in/master out ? eusci_a0 spi mode uca0somi l3 42 33 25 i/o slave out/master in ? eusci_a0 spi mode uca0ste b3 17 13 10 i/o slave transmit enable ? eusci_a0 spi mode uca1clk k11 64 52 40 i/o clock signal input ? eusci_a1 spi slave mode clock signal output ? eusci_a1 spi master mode uca1simo g4 35 28 20 i/o slave in/master out ? eusci_a1 spi mode uca1somi h1 36 29 21 i/o slave out/master in ? eusci_a1 spi mode uca1ste j11 63 51 39 i/o slave transmit enable ? eusci_a1 spi mode uca2clk g10 67 55 ? i/o clock signal input ? eusci_a2 spi slave mode clock signal output ? eusci_a2 spi master mode uca2simo j10 65 53 ? i/o slave in/master out ? eusci_a2 spi mode uca2somi h10 66 54 ? i/o slave out/master in ? eusci_a2 spi mode uca2ste g8 68 56 ? i/o slave transmit enable ? eusci_a2 spi mode uca3clk a6 10 ? ? i/o clock signal input ? eusci_a3 spi slave mode clock signal output ? eusci_a3 spi master mode uca3simo d8 8 ? ? i/o slave in/master out ? eusci_a3 spi mode uca3somi d7 9 ? ? i/o slave out/master in ? eusci_a3 spi mode uca3ste b6 11 ? ? i/o slave transmit enable ? eusci_a3 spi mode ucb0clk k3 43 34 26 i/o clock signal input ? eusci_b0 spi slave mode clock signal output ? eusci_b0 spi master mode ucb0simo l6 51 39 31 i/o slave in/master out ? eusci_b0 spi mode ucb0somi k6 52 40 32 i/o slave out/master in ? eusci_b0 spi mode ucb0ste a4 16 12 9 i/o slave transmit enable ? eusci_b0 spi mode ucb1clk k8 55 43 ? i/o clock signal input ? eusci_b1 spi slave mode clock signal output ? eusci_b1 spi master mode ucb1simo l7 53 41 ? i/o slave in/master out ? eusci_b1 spi mode ucb1somi k7 54 42 ? i/o slave out/master in ? eusci_b1 spi mode ucb1ste l8 56 44 ? i/o slave transmit enable ? eusci_b1 spi mode ucb2clk d1 25 21 ? i/o clock signal input ? eusci_b2 spi slave mode clock signal output ? eusci_b2 spi master mode ucb2simo a5 13 9 ? i/o slave in/master out ? eusci_b2 spi mode ucb2somi b5 14 10 ? i/o slave out/master in ? eusci_b2 spi mode ucb2ste d4 26 22 ? i/o slave transmit enable ? eusci_b2 spi mode ucb3clk e8 71 ? ? i/o clock signal input ? eusci_b3 spi slave mode clock signal output ? eusci_b3 spi master mode ucb3simo f8 69 ? ? i/o slave in/master out ? eusci_b3 spi mode ucb3somi f10 70 ? ? i/o slave out/master in ? eusci_b3 spi mode ucb3ste c10 72 ? ? i/o slave transmit enable ? eusci_b3 spi mode system nmi j2 38 31 23 i nonmaskable interrupt input rst j2 38 31 23 i reset input active low
24 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 terminal configuration and functions copyright ? 2016 ? 2017, texas instruments incorporated table 4-2. signal descriptions (continued) function signal name pin no. (1) pin type (2) description zvw pn pm rgz timer ta0.0 l6 51 39 31 i/o ta0 ccr0 capture: cci0a input, compare: out0 ta0.0 j11 63 51 39 i/o ta0 ccr0 capture: cci0b input, compare: out0 ta0.1 a10 1 1 1 i/o ta0 ccr1 capture: cci1a input, compare: out1 ta0.2 a9 2 2 2 i/o ta0 ccr2 capture: cci2a input, compare: out2 ta0clk b9 3 3 3 i ta0 input clock ta1.0 k6 52 40 32 i/o ta1 ccr0 capture: cci0a input, compare: out0 ta1.0 k11 64 52 40 i/o ta1 ccr0 capture: cci0b input, compare: out0 ta1.1 b9 3 3 3 i/o ta1 ccr1 capture: cci1a input, compare: out1 ta1.2 a4 16 12 9 i/o ta1 ccr2 capture: cci2a input, compare: out2 ta1clk a9 2 2 2 i ta1 input clock ta4.0 e1 27 23 ? i/o ta4 ccr0 capture: cci0b input, compare: out0 ta4.0 g10 67 55 ? i/o ta4 ccr0 capture: cci0a input, compare: out0 ta4.1 d4 26 22 ? i/o ta4ccr1 capture: cci1b input, compare: out1 ta4.1 g8 68 56 ? i/o ta4 ccr1 capture: cci1a input, compare: out1 ta4clk k8 55 43 ? i ta4 input clock tb0.0 g4 35 28 20 i/o tb0 ccr0 capture: cci0b input, compare: out0 tb0.0 l3 42 33 25 i/o tb0 ccr0 capture: cci0a input, compare: out0 tb0.1 b3 17 13 10 i/o tb0 ccr1 capture: cci1a input, compare: out1 tb0.1 h1 36 29 21 o tb0 ccr1 compare: out1 tb0.2 b4 18 14 11 i/o tb0 ccr2 capture: cci2a input, compare: out2 tb0.2 k3 43 34 26 o tb0 ccr2 compare: out2 tb0.3 k5 47 35 27 i/o tb0 ccr3 capture: cci3a input, compare: out3 tb0.3 l6 51 39 31 i/o tb0 ccr3 capture: cci3b input, compare: out3 tb0.4 l5 48 36 28 i/o tb0 ccr4 capture: cci4a input, compare: out4 tb0.4 k6 52 40 32 i/o tb0 ccr4 capture: cci4b input, compare: out4 tb0.5 h5 49 37 29 i/o tb0 ccr5 capture: cci5a input, compare: out5 tb0.5 h7 57 45 33 i/o tb0ccr5 capture: cci5b input, compare: out5 tb0.6 l2 41 32 24 i/o tb0 ccr6 capture: cci6b input, compare: out6 tb0.6 h6 50 38 30 i/o tb0 ccr6 capture: cci6a input, compare: out6 tb0clk l2 41 32 24 i tb0 clock input tb0outh b1 j10 21 65 17 53 12 i switch all pwm outputs high impedance input ? tb0 uart uca0rxd l3 42 33 25 i receive data ? eusci_a0 uart mode uca0txd l2 41 32 24 o transmit data ? eusci_a0 uart mode uca1rxd h1 36 29 21 i receive data ? eusci_a1 uart mode uca1txd g4 35 28 20 o transmit data ? eusci_a1 uart mode uca2rxd h10 66 54 ? i receive data ? eusci_a2 uart mode uca2txd j10 65 53 ? o transmit data ? eusci_a2 uart mode uca3rxd d7 9 ? ? i receive data ? eusci_a3 uart mode uca3txd d8 8 ? ? o transmit data ? eusci_a3 uart mode
25 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 terminal configuration and functions copyright ? 2016 ? 2017, texas instruments incorporated (1) n/a = not applicable (2) this is a switch, not a buffer. (3) only for input pins (4) this is supply input, not a buffer. 4.4 pin multiplexing pin multiplexing for these devices is controlled by both register settings and operating modes (for example, if the device is in test mode). for details of the settings for each pin and schematics of the multiplexed ports, see section 6.13 . 4.5 buffer types table 4-3 describes the buffer types that are referenced in table 4-1 . table 4-3. buffer type buffer type (standard) nominal voltage hysteresis pu or pd (1) nominal pu or pd strength ( a) (1) output drive strength (ma) (1) comments analog (2) 3.0 v no n/a n/a n/a see analog modules in specifications for details lvcmos 3.0 v yes (3) programmable see digital i/os see typical characteristics ? outputs power (dvcc) (4) 3.0 v no n/a n/a n/a svs enables hysteresis on dvcc power (avcc) (4) 3.0 v no n/a n/a n/a power (dvss and avss) (4) 0 v no n/a n/a n/a (1) for any unused pin with a secondary function that is shared with general-purpose i/o, follow the guidelines for the px.0 to px.7 pins. (2) the pulldown capacitor should not exceed 2.2 nf when using devices with spy-bi-wire interface in spy-bi-wire mode or in 4-wire jtag mode with ti tools like fet interfaces or gang programmers. 4.6 connection of unused pins table 4-4 lists the correct termination of all unused pins. table 4-4. connection of unused pins (1) pin potential comment avcc dv cc avss dv ss px.0 to px.7 open switched to port function, output direction (pxdir.n = 1) rst/nmi dv cc or v cc 47-k ? pullup or internal pullup selected with 10-nf (2.2 nf (2) ) pulldown pj.0/tdo pj.1/tdi pj.2/tms pj.3/tck open the jtag pins are shared with general-purpose i/o function (pj.x). if not being used, these should be switched to port function, output direction. when used as jtag pins, these pins should remain open. test open this pin always has an internal pulldown enabled.
26 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) voltage differences between dvcc and avcc exceeding the specified limits may cause malfunction of the device including erroneous writes to ram and fram. (3) all voltages referenced to v ss . (4) higher temperature may be applied during board soldering according to the current jedec j-std-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. 5 specifications 5.1 absolute maximum ratings (1) over operating free-air temperature range (unless otherwise noted) min max unit voltage applied at dvcc and avcc pins to v ss ? 0.3 4.1 v voltage difference between dvcc and avcc pins (2) 0.3 v voltage applied to any pin (3) ? 0.3 v cc + 0.3 v (4.1 v max) v diode current at any device pin 2 ma storage temperature, t stg (4) ? 40 125 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. pins listed as 1000 v may actually have higher performance. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. pins listed as 250 v may actually have higher performance. 5.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 1000 v charged-device model (cdm), per jedec specification jesd22-c101 (2) 250
27 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated (1) ti recommends powering avcc and dvcc pins from the same source. at a minimum, during power up, power down, and device operation, the voltage difference between avcc and dvcc must not exceed the limits specified under absolute maximum ratings . exceeding the specified limits may cause malfunction of the device including erroneous writes to ram and fram. (2) fast supply voltage changes can trigger a bor reset even within the recommended supply voltage range. to avoid unwanted bor resets, the supply voltage must change by less than 0.05 v per microsecond ( 0.05 v/ s). following the data sheet recommendation for capacitor c dvcc should limit the slopes accordingly. (3) modules may have a different supply voltage range specification. see the specification of the respective module in this data sheet. (4) the minimum supply voltage is defined by the supervisor svs levels. see the pmm svs threshold parameters for the exact values. (5) for each supply pin pair (dvcc and dvss, avcc and avss), place a low-esr ceramic capacitor of 100 nf (minimum) as close as possible (within a few millimeters) to the respective pin pairs. (6) modules may have a different maximum input clock specification. see the specification of the respective module in this data sheet. (7) dco settings and hf cyrstals with a typical value less than or equal to the specified max value are permitted. (8) wait states only occur on actual fram accesses; that is, on fram cache misses. ram and peripheral accesses are always excecuted without wait states. (9) dco settings and hf cyrstals with a typical value less than or equal to the specified max value are permitted. if a clock sources with a higher typical value is used, the clock must be divided in the clock system. 5.3 recommended operating conditions typ data are based on v cc = 3.0 v and t a = 25 c, unless otherwise noted min nom max unit v cc supply voltage range applied at all dvcc and avcc pins (1) (2) (3) 1.8 (4) 3.6 v v ss supply voltage applied at all dvss and avss pins. 0 v t a operating free-air temperature ? 40 85 c t j operating junction temperature ? 40 85 c c dvcc capacitor value at dvcc (5) 1 ? 20% f f system processor frequency (maximum mclk frequency) (6) no fram wait states (nwaitsx = 0) 0 8 (7) mhz with fram wait states (nwaitsx = 1) (8) 0 16 (9) f aclk maximum aclk frequency 50 khz f smclk maximum smclk frequency 16 (9) mhz
28 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated (1) all inputs are tied to 0 v or to v cc . outputs do not source or sink any current. (2) characterized with program executing typical data processing. f aclk = 32768 hz, f mclk = f smclk = f dco at specified frequency, except for 12 mhz. for 12 mhz, f dco = 24 mhz and f mclk = f smclk = f dco / 2. at mclk frequencies above 8 mhz, the fram requires wait states. when wait states are required, the effective mclk frequency (f mclk,eff ) decreases. the effective mclk frequency also depends on the cache hit ratio. smclk is not affected by the number of wait states or the cache hit ratio. the following equation can be used to compute f mclk,eff : f mclk,eff = f mclk / [wait states (1 ? cache hit ratio) + 1] for example, with 1 wait state and 75% cache hit ratio f mckl,eff = f mclk / [1 (1 ? 0.75) + 1] = f mclk / 1.25. (3) represents typical program execution. program and data reside entirely in fram. all execution is from fram. (4) program resides in fram. data resides in sram. average current dissipation varies with cache hit-to-miss ratio as specified. cache hit ratio represents number cache accesess divided by the total number of fram accesses. for example, a 75% ratio implies three of every four accesses is from cache, and the remaining are fram accesses. (5) see figure 5-1 for typical curves. the characteristic equation shown in the graph is computed using the least squares method for best linear fit using the typical data shown in section 5.4 . (6) program and data reside entirely in ram. all execution is from ram. (7) program and data reside entirely in ram. all execution is from ram. fram is off. 5.4 active mode supply current into v cc excluding external current over recommended operating free-air temperature (unless otherwise noted) (1) (2) (see figure 5-1 ) parameter execution memory v cc frequency (f mclk = f smclk ) unit 1 mhz 0 wait states (nwaitsx = 0) 4 mhz 0 wait states (nwaitsx = 0) 8 mhz 0 wait states (nwaitsx = 0) 12 mhz 1 wait state (nwaitsx = 1) 16 mhz 1 wait state (nwaitsx = 1) typ max typ max typ max typ max typ max i am, fram_uni (unified memory) (3) fram 3.0 v 225 665 1275 1550 1970 a i am, fram (0%) (4) (5) fram 0% cache hit ratio 3.0 v 420 1455 2850 2330 3000 a i am, fram (50%) (4) (5) fram 50% cache hit ratio 3.0 v 275 855 1650 1770 2265 a i am, fram (66%) (4) (5) fram 66% cache hit ratio 3.0 v 220 650 1240 1490 1880 a i am, fram (75%) (4) (5) fram 75% cache hit ratio 3.0 v 192 261 535 1015 1170 1290 1490 1620 1870 a i am, fram (100% (4) (5) fram 100% cache hit ratio 3.0 v 125 255 450 670 790 a i am, ram (6) (5) ram 3.0 v 140 325 590 880 1070 a i am, ram only (7) (5) ram 3.0 v 90 182 280 540 830 1020 1313 a
29 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated 5.5 typical characteristics, active mode supply currents figure 5-1. typical active mode supply currents, no wait states (1) all inputs are tied to 0 v or to v cc . outputs do not source or sink any current. (2) current for watchdog timer clocked by smclk included. f aclk = 32768 hz, f mclk = 0 mhz, f smclk = f dco at specified frequency - except for 12 mhz: here f dco =24mhz and f smclk = f dco / 2. 5.6 low-power mode (lpm0, lpm1) supply currents into v cc excluding external current over recommended operating free-air temperature (unless otherwise noted) (1) (2) parameter v cc frequency (f smclk ) unit 1 mhz 4 mhz 8 mhz 12 mhz 16 mhz typ max typ max typ max typ max typ max i lpm0 2.2 v 75 105 165 240 220 a 3.0 v 85 135 115 175 250 240 290 i lpm1 2.2 v 40 65 130 215 195 a 3.0 v 40 67 65 130 215 195 222 f mclk , mclk frequency (mhz) i am , active mode current (a) 1 2 3 4 5 6 7 8 0 500 1000 1500 2000 2500 3000 i (am,75%) [a] = 118 f [mhz] + 74 i (am,0%) i (am,50%) i (am,66%) i (am,75%) i (am,100%) i (am,ram)
30 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated (1) all inputs are tied to 0 v or to v cc . outputs do not source or sink any current. (2) not applicable for devices with hf crystal oscillator only. (3) characterized with a micro crystal ms1v-t1k crystal with a load capacitance of 12.5 pf. the internal and external load capacitance are chosen to closely match the required 12.5 pf load. (4) low-power mode 2, crystal oscillator test conditions: current for watchdog timer clocked by aclk and rtc clocked by xt1 included. current for brownout and svs included. cpuoff = 1, scg0 = 0 scg1 = 1, oscoff = 0 (lpm2), f xt1 = 32768 hz, f aclk = f xt1 , f mclk = f smclk = 0 mhz (5) characterized with a seiko ssp-t7-fl (smd) crystal with a load capacitance of 3.7 pf. the internal and external load capacitance are chosen to closely match the required 3.7-pf load. (6) low-power mode 2, vlo test conditions: current for watchdog timer clocked by aclk included. rtc disabled (rtchold = 1). current for brownout and svs included. cpuoff = 1, scg0 = 0 scg1 = 1, oscoff = 0 (lpm2), f xt1 = 0 hz, f aclk = f vlo , f mclk = f smclk = 0 mhz (7) low-power mode 3, 12-pf crystal including svs test conditions: current for watchdog timer clocked by aclk and rtc clocked by xt1 included. current for brownout and svs included (svshe = 1). cpuoff = 1, scg0 = 1 scg1 = 1, oscoff = 0 (lpm3), f xt1 = 32768 hz, f aclk = f xt1 , f mclk = f smclk = 0 mhz activating additional peripherals increases the current consumption due to active supply current contribution and due to additional idle current. see the idle currents specified for the respective peripheral groups. (8) low-power mode 3, 3.7-pf crystal excluding svs test conditions: current for watchdog timer clocked by aclk and rtc clocked by xt1 included. current for brownout included. svs disabled (svshe = 0). cpuoff = 1, scg0 = 1 scg1 = 1, oscoff = 0 (lpm3), f xt1 = 32768 hz, f aclk = f xt1 , f mclk = f smclk = 0 mhz activating additional peripherals increases the current consumption due to active supply current contribution and due to additional idle current. see the idle currents specified for the respective peripheral groups. (9) low-power mode 3, vlo excluding svs test conditions: current for watchdog timer clocked by aclk included. rtc disabled (rtchold = 1). ram disabled (rcctl0 = 5a55h). current for brownout included. svs disabled (svshe = 0). cpuoff = 1, scg0 = 1 scg1 = 1, oscoff = 0 (lpm3), f xt1 = 0 hz, f aclk = f vlo , f mclk = f smclk = 0 mhz activating additional peripherals increases the current consumption due to active supply current contribution and due to additional idle current. see the idle currents specified for the respective peripheral groups. (10) low-power mode 4 including svs test conditions: current for brownout and svs included (svshe = 1). cpuoff = 1, scg0 = 1 scg1 = 1, oscoff = 1 (lpm4), f xt1 = 0 hz, f aclk = 0 hz, f mclk = f smclk = 0 mhz activating additional peripherals increases the current consumption due to active supply current contribution and due to additional idle current. see the idle currents specified for the respective peripheral groups. 5.7 low-power mode (lpm2, lpm3, lpm4) supply currents (into v cc ) excluding external current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see figure 5-2 and figure 5-3 ) parameter v cc ? 40 c 25 c 60 c 85 c unit typ max typ max typ max typ max i lpm2,xt12 low-power mode 2, 12-pf crystal (2) (3) (4) 2.2 v 0.8 1.3 4.1 10.8 a 3.0 v 0.8 1.3 2.7 4.1 10.8 25 i lpm2,xt3.7 low-power mode 2, 3.7-pf crystal (2) (5) (4) 2.2 v 0.6 1.2 4.0 10.7 a 3.0 v 0.6 1.2 4.0 10.7 i lpm2,vlo low-power mode 2, vlo, includes svs (6) 2.2 v 0.5 1.0 3.8 10.5 a 3.0 v 0.5 1.0 2.4 3.8 10.5 24.5 i lpm3,xt12 low-power mode 3, 12-pf crystal, includes svs (2) (3) (7) 2.2 v 0.8 1.0 2.2 4.5 a 3.0 v 0.8 1.0 1.5 2.2 4.5 9.9 i lpm3,xt3.7 low-power mode 3, 3.7-pf crystal, excludes svs (2) (5) (8) (also see figure 5-2 ) 2.2 v 0.5 0.7 2.1 4.4 a 3.0 v 0.5 0.7 2.1 4.4 i lpm3,vlo low-power mode 3, vlo, excludes svs (9) 2.2 v 0.4 0.5 1.9 4.2 a 3.0 v 0.4 0.5 1.2 1.9 4.2 9.5 i lpm3,vlo, ramoff low-power mode 3, vlo, excludes svs, ram powered down completely (9) 2.2 v 0.36 0.47 1.4 2.6 a 3.0 v 0.36 0.47 1.1 1.4 2.6 7.9 i lpm4,svs low-power mode 4, includes svs (10) 2.2 v 0.5 0.6 1.9 4.3 a 3.0 v 0.5 0.6 1.2 1.9 4.3 9.5
31 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated low-power mode (lpm2, lpm3, lpm4) supply currents (into v cc ) excluding external current (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see figure 5-2 and figure 5-3 ) parameter v cc ? 40 c 25 c 60 c 85 c unit typ max typ max typ max typ max (11) low-power mode 4 excluding svs test conditions: current for brownout included. svs disabled (svshe = 0). ram disabled (rcctl0 = 5a55h). cpuoff = 1, scg0 = 1 scg1 = 1, oscoff = 1 (lpm4), f xt1 = 0 hz, f aclk = 0 hz, f mclk = f smclk = 0 mhz activating additional peripherals increases the current consumption due to active supply current contribution and due to additional idle current. see the idle currents specified for the respective peripheral groups. i lpm4 low-power mode 4, excludes svs (11) 2.2 v 0.3 0.4 1.7 4.0 a 3.0 v 0.3 0.4 1.1 1.7 4.0 9.3 i lpm4,ramoff low-power mode 4, excludes svs, ram powered down completely (11) 2.2 v 0.3 0.37 1.2 2.5 a 3.0 v 0.3 0.37 1.0 1.2 2.5 7.8 i idle,groupa additional idle current if one or more modules from group a (see table 6-3 ) are activated in lpm3 or lpm4 3.0 v 0.02 0.3 1.6 a i idle,groupb additional idle current if one or more modules from group b (see table 6-3 ) are activated in lpm3 or lpm4 3.0 v 0.02 0.35 2.1 a i idle,groupc additional idle current if one or more modules from group c (see table 6-3 ) are activated in lpm3 or lpm4 3.0 v 0.02 0.38 2.3 a
32 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated (1) all inputs are tied to 0 v or to v cc . outputs do not source or sink any current. (2) not applicable for devices with hf crystal oscillator only. (3) characterized with a micro crystal ms1v-t1k crystal with a load capacitance of 12.5 pf. the internal and external load capacitance are chosen to closely match the required 12.5 pf load. (4) low-power mode 3.5, 1-pf crystal including svs test conditions: current for rtc clocked by xt1 included. current for brownout and svs included (svshe = 1). core regulator disabled. pmmregoff = 1; cpuoff = 1, scg0 = 1 scg1 = 1, oscoff = 1 (lpmx.5), f xt1 = 32768 hz, f aclk = f xt1 , f mclk = f smclk = 0 mhz (5) characterized with a seiko ssp-t7-fl (smd) crystal with a load capacitance of 3.7 pf. the internal and external load capacitance are chosen to closely match the required 3.7-pf load. (6) low-power mode 3.5, 3.7-pf crystal excluding svs test conditions: current for rtc clocked by xt1 included.current for brownout included. svs disabled (svshe = 0). core regulator disabled. pmmregoff = 1; cpuoff = 1, scg0 = 1 scg1 = 1, oscoff = 1 (lpmx.5), f xt1 = 32768 hz, f aclk = f xt1 , f mclk = f smclk = 0 mhz (7) low-power mode 4.5 including svs test conditions: current for brownout and svs included (svshe = 1). core regulator disabled. pmmregoff = 1; cpuoff = 1, scg0 = 1 scg1 = 1, oscoff = 1 (lpmx.5), f xt1 = 0 hz, f aclk = 0 hz, f mclk = f smclk = 0 mhz (8) low-power mode 4.5 excluding svs test conditions: current for brownout included. svs disabled (svshe = 0). core regulator disabled. pmmregoff = 1; cpuoff = 1, scg0 = 1 scg1 = 1, oscoff = 1 (lpmx.5), f xt1 = 0 hz, f aclk = 0 hz, f mclk = f smclk = 0 mhz 5.8 low-power mode (lpmx.5) supply currents (into v cc ) excluding external current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see figure 5-4 and figure 5-5 ) parameter v cc ? 40 c 25 c 60 c 85 c unit typ max typ max typ max typ max i lpm3.5,xt12 low-power mode 3.5, 12-pf crystal including svs (2) (3) (4) 2.2 v 0.45 0.5 0.55 0.75 a 3.0 v 0.45 0.5 0.72 0.55 0.75 1.65 i lpm3.5,xt3.7 low-power mode 3.5, 3.7-pf crystal excluding svs (2) (5) (6) 2.2 v 0.3 0.35 0.4 0.65 a 3.0 v 0.3 0.35 0.4 0.65 i lpm4.5,svs low-power mode 4.5, including svs (7) 2.2 v 0.23 0.25 0.28 0.4 a 3.0 v 0.23 0.25 0.42 0.28 0.4 0.75 i lpm4.5 low-power mode 4.5, excluding svs (8) 2.2 v 0.035 0.045 0.075 0.15 a 3.0 v 0.035 0.045 0.075 0.15 0.55
33 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated 5.9 typical characteristics, low-power mode supply currents figure 5-2. lpm3 supply current vs temperature figure 5-3. lpm4 supply current vs temperature figure 5-4. lpm3.5 supply current vs temperature figure 5-5. lpm4.5 supply current vs temperature temperature (c) i lpm3.5 , lpm3.5 supply current (a) -40 -20 0 20 40 60 80 100 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 2.2 v, svs off 3.0 v, svs off temperature (c) i lpm4.5 , lpm4.5 supply current (a) -40 -20 0 20 40 60 80 100 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 2.2 v, svs off 3.0 v, svs off 2.2 v, svs on 3.0 v, svs on temperature (c) i lpm3 , lpm3 supply current (a) -40 -20 0 20 40 60 80 100 0.5 1 1.5 2 2.5 3 3.5 3.0 v, svs off 2.2 v, svs off 3.0 v, svs on 2.2 v, svs on temperature (c) i lpm4 , lpm4 supply current (a) -40 -20 0 20 40 60 80 100 0 0.5 1 1.5 2 2.5 3 3.0 v, svs off 2.2 v, svs off 3.0 v, svs on 2.2 v, svs on
34 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated (1) for other module currents not listed here, see the module-specific parameter sections. 5.10 typical characteristics, current consumption per module (1) module test conditions reference clock min typ max unit timer_a module input clock 3 a/mhz timer_b module input clock 5 a/mhz eusci_a uart mode module input clock 6.3 a/mhz eusci_a spi mode module input clock 4 a/mhz eusci_b spi mode module input clock 4 a/mhz eusci_b i 2 c mode, 100 kbaud module input clock 4 a/mhz rtc_c 32 khz 100 na mpy only from start to end of operation mclk 28 a/mhz crc16 only from start to end of operation mclk 3.3 a/mhz crc32 only from start to end of operation mclk 3.3 a/mhz lea 256 point complex fft, data = nonzero mclk 86 a/mhz 256 point complex fft, data = zero 66 (1) for more information about traditional and new thermal metrics, see semiconductor and ic package thermal metrics . (2) these values are based on a jedec-defined 2s2p system (with the exception of the theta jc (r jc ) value, which is based on a jedec-defined 1s0p system) and will change based on environment and application. for more information, see these eia/jedec standards: ? jesd51-2, integrated circuits thermal test method environmental conditions - natural convection (still air) ? jesd51-3, low effective thermal conductivity test board for leaded surface mount packages ? jesd51-7, high effective thermal conductivity test board for leaded surface mount packages ? jesd51-9, test boards for area array surface mount package thermal measurements 5.11 thermal packaging characteristics thermal metric (1) (2) package value unit r ja junction-to-ambient thermal resistance, still air qfn-48 (rgz) 27.5 c/w r jc(top) junction-to-case (top) thermal resistance 12.5 c/w r jb junction-to-board thermal resistance 4.4 c/w jb junction-to-board thermal characterization parameter 4.4 c/w jt junction-to-top thermal characterization parameter 0.2 c/w r jc(bottom) junction-to-case (bottom) thermal resistance 0.8 c/w r ja junction-to-ambient thermal resistance, still air qfp-64 (pm) 53.2 c/w r jc(top) junction-to-case (top) thermal resistance 14.3 c/w r jb junction-to-board thermal resistance 24.7 c/w jb junction-to-board thermal characterization parameter 24.4 c/w jt junction-to-top thermal characterization parameter 0.6 c/w r ja junction-to-ambient thermal resistance, still air qfp-80 (pn) 47.9 c/w r jc(top) junction-to-case (top) thermal resistance 13.0 c/w r jb junction-to-board thermal resistance 22.5 c/w jb junction-to-board thermal characterization parameter 22.2 c/w jt junction-to-top thermal characterization parameter 0.6 c/w r ja junction-to-ambient thermal resistance, still air bga-87 (zvw) 60.6 c/w r jc(top) junction-to-case (top) thermal resistance 18.1 c/w r jb junction-to-board thermal resistance 31.8 c/w jb junction-to-board thermal characterization parameter 30.1 c/w jt junction-to-top thermal characterization parameter 0.7 c/w
35 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated 5.12 timing and switching characteristics 5.12.1 power supply sequencing ti recommends powering avcc and dvcc pins from the same source. at a minimum, during power up, power down, and device operation, the voltage difference between avcc and dvcc must not exceed the limits specified in absolute maximum ratings . exceeding the specified limits may cause malfunction of the device including erroneous writes to ram and fram. table 5-1 lists the power ramp requirements. (1) fast supply voltage changes can trigger a bor reset even within the recommended supply voltage range. to avoid unwanted bor resets, the supply voltage must change by less than 0.05 volts per microsecond ( 0.05 v/ s). following the data sheet recommendation for capacitor c dvcc should limit the slopes accordingly. (2) the brownout levels are measured with a slowly changing supply. table 5-1. brownout and device reset power ramp requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min max unit v vcc_bor ? brownout power-down level (1) | ddv cc /d t | < 3 v/s 0.73 1.66 v v vcc_bor+ brownout power-up level (1) | ddv cc /d t | < 3 v/s (2) 0.79 1.75 v table 5-2 lists the supply voltage supervisor characteristics. table 5-2. svs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit i svsh,lpm svs h current consumption, low power modes 170 300 na v svsh- svs h power-down level 1.75 1.80 1.85 v v svsh+ svs h power-up level 1.77 1.88 1.99 v v svsh_hys svs h hysteresis 40 150 mv t pd,svsh, am svs h propagation delay, active mode dv vcc /dt = ? 10 mv/ s 10 s
36 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated 5.12.2 reset timing table 5-3 lists the input requirements of the reset pin. (1) not applicable if rst/nmi pin configured as nmi. table 5-3. reset input over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) v cc min max unit t (rst) external reset pulse duration on rst (1) 2.2 v, 3.0 v 2 s 5.12.3 clock specifications lfxtclk (see table 5-4 ) is a low-frequency oscillator that can be used either with low-frequency 32768- hz watch crystals, standard crystals, resonators, or external clock sources in the 50 khz or below range. when in bypass mode, lfxtclk can be driven with an external square-wave signal. (1) to improve emi on the lfxt oscillator, the following guidelines should be observed. ? keep the trace between the device and the crystal as short as possible. ? design a good ground plane around the oscillator pins. ? prevent crosstalk from other clock or data lines into oscillator pins lfxin and lfxout. ? avoid running pcb traces underneath or adjacent to the lfxin and lfxout pins. ? use assembly materials and processes that avoid any parasitic load on the oscillator lfxin and lfxout pins. ? if conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins. (2) when lfxtbypass is set, lfxt circuits are automatically powered down. input signal is a digital square wave with parametrics defined in the schmitt-trigger inputs section of this datasheet. duty cycle requirements are defined by dc lfxt, sw . (3) maximum frequency of operation of the entire device cannot be exceeded. (4) oscillation allowance is based on a safety factor of 5 for recommended crystals. the oscillation allowance is a function of the lfxtdrive settings and the effective load. in general, comparable oscillator allowance can be achieved based on the following guidelines, but should be evaluated based on the actual crystal selected for the application: ? for lfxtdrive = {0}, c l,eff = 3.7 pf. ? for lfxtdrive = {1}, c l,eff = 6 pf ? for lfxtdrive = {2}, 6 pf c l,eff 9 pf ? for lfxtdrive = {3}, 9 pf c l,eff 12.5 pf table 5-4. low-frequency crystal oscillator, lfxt (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit i vcc.lfxt current consumption f osc = 32768 hz, lfxtbypass = 0, lfxtdrive = {0}, t a = 25 c, c l,eff = 3.7 pf, esr 44 k 3.0 v 180 na f osc = 32768 hz. lfxtbypass = 0, lfxtdrive = {1}, t a = 25 c, c l,eff = 6 pf, esr 40 k 3.0 v 185 na f osc = 32768 hz lfxtbypass = 0, lfxtdrive = {2}, t a = 25 c, c l,eff = 9 pf, esr 40 k 3.0 v 225 na f osc = 32768 hz lfxtbypass = 0, lfxtdrive = {3}, t a = 25 c, c l,eff = 12.5 pf, esr 40 k 3.0 v 330 na f lfxt lfxt oscillator crystal frequency lfxtbypass = 0 32768 hz dc lfxt lfxt oscillator duty cycle measured at aclk, f lfxt = 32768 hz 30% 70% f lfxt,sw lfxt oscillator logic-level square-wave input frequency lfxtbypass = 1 (2) (3) 10.5 32.768 50 khz dc lfxt, sw lfxt oscillator logic-level square-wave input duty cycle lfxtbypass = 1 30% 70% oa lfxt oscillation allowance for lf crystals (4) lfxtbypass = 0, lfxtdrive = {1}, f lfxt = 32768 hz, c l,eff = 6 pf 210 k ? lfxtbypass = 0, lfxtdrive = {3}, f lfxt = 32768 hz, c l,eff = 12.5 pf 300
37 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated table 5-4. low-frequency crystal oscillator, lfxt (1) (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit (5) this represents all the parasitic capacitance present at the lfxin and lfxout terminals, respectively, including parasitic bond and package capacitance. the effective load capacitance, c l,eff can be computed as c in c out / (c in + c out ), where c in and c out are the total capacitance at the lfxin and lfxout terminals, respectively. (6) requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. recommended effective load capacitance values supported are 3.7 pf, 6 pf, 9 pf, and 12.5 pf. maximum shunt capacitance of 1.6 pf. the pcb adds additional capacitance, so it must also be considered in the overall capacitance. verify that the recommended effective load capacitance of the selected crystal is met. (7) includes startup counter of 1024 clock cycles. (8) frequencies above the max specification do not set the fault flag. frequencies between the min and max specification may set the flag. a static condition or stuck at fault condition will set the flag. (9) measured with logic-level input frequency but also applies to operation with crystals. c lfxin integrated load capacitance at lfxin terminal (5) (6) 2 pf c lfxout integrated load capacitance at lfxout terminal (5) (6) 2 pf t start,lfxt start-up time (7) f osc = 32768 hz lfxtbypass = 0, lfxtdrive = {0}, t a = 25 c, c l,eff = 3.7 pf, 3.0 v 800 ms f osc = 32768 hz lfxtbypass = 0, lfxtdrive = {3}, t a = 25 c, c l,eff = 12.5 pf 3.0 v 1000 f fault,lfxt oscillator fault frequency (8) (9) 0 3500 hz hfxtclk (see table 5-5 ) is a high-frequency oscillator that can be used with standard crystals or resonators in the 4 ? mhz to 24-mhz range. when in bypass mode, hfxtclk can be driven with an external square-wave signal. (1) to improve emi on the hfxt oscillator the following guidelines should be observed. ? keep the traces between the device and the crystal as short as possible. ? design a good ground plane around the oscillator pins. ? prevent crosstalk from other clock or data lines into oscillator pins hfxin and hfxout. ? avoid running pcb traces underneath or adjacent to the hfxin and hfxout pins. ? use assembly materials and processes that avoid any parasitic load on the oscillator hfxin and hfxout pins. ? if conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins. (2) hffreq = {0} is not supported for hfxt crystal mode of operation. (3) maximum frequency of operation of the entire device cannot be exceeded. table 5-5. high-frequency crystal oscillator, hfxt (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit i dvcc.hfxt hfxt oscillator crystal current hf mode at typical esr f osc = 4 mhz, hfxtbypass = 0, hfxtdrive = 0, hffreq = 1 (2) , t a = 25 c, c l,eff = 18 pf, typical esr, c shunt 3.0 v 75 a f osc = 8 mhz, hfxtbypass = 0, hfxtdrive = 1, hffreq = 1, t a = 25 c, c l,eff = 18 pf, typical esr, c shunt 120 f osc = 16 mhz, hfxtbypass = 0, hfxtdrive = 2, hffreq = 2, t a = 25 c c l,eff = 18 pf, typical esr, c shunt 190 f osc = 24 mhz hfxtbypass = 0, hfxtdrive = 3, hffreq = 3, t a = 25 c c l,eff = 18 pf, typical esr, c shunt 250 f hfxt hfxt oscillator crystal frequency, crystal mode hfxtbypass = 0, hffreq = 1 (2) (3) 4 8 mhz hfxtbypass = 0, hffreq = 2 (3) 8.01 16 hfxtbypass = 0, hffreq = 3 (3) 16.01 24
38 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated table 5-5. high-frequency crystal oscillator, hfxt (1) (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit (4) when hfxtbypass is set, hfxt circuits are automatically powered down. input signal is a digital square wave with parametrics defined in the schmitt-trigger inputs section of this datasheet. duty cycle requirements are defined by dc hfxt, sw . (5) oscillation allowance is based on a safety factor of 5 for recommended crystals. (6) includes startup counter of 1024 clock cycles. (7) this represents all the parasitic capacitance present at the hfxin and hfxout terminals, respectively, including parasitic bond and package capacitance. the effective load capacitance, c l,eff can be computed as c in c out / (c in + c out ), where c in and c out is the total capacitance at the hfxin and hfxout terminals, respectively. (8) requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. recommended effective load capacitance values supported are 14 pf, 16 pf, and 18 pf. maximum shunt capacitance of 7 pf. the pcb adds additional capacitance, so it must also be considered in the overall capacitance. verify that the recommended effective load capacitance of the selected crystal is met. (9) frequencies above the max specification do not set the fault flag. frequencies between the min and max might set the flag. a static condition or stuck at fault condition will set the flag. (10) measured with logic-level input frequency but also applies to operation with crystals. dc hfxt hfxt oscillator duty cycle. measured at smclk, f hfxt = 16 mhz 40% 50% 60% f hfxt,sw hfxt oscillator logic-level square-wave input frequency, bypass mode hfxtbypass = 1, hffreq = 0 (4) (3) 0.9 4 mhz hfxtbypass = 1, hffreq = 1 (4) (3) 4.01 8 hfxtbypass = 1, hffreq = 2 (4) (3) 8.01 16 hfxtbypass = 1, hffreq = 3 (4) (3) 16.01 24 dc hfxt, sw hfxt oscillator logic-level square-wave input duty cycle hfxtbypass = 1 40% 60% oa hfxt oscillation allowance for hfxt crystals (5) hfxtbypass = 0, hfxtdrive = 0, hffreq = 1 (2) , f hfxt,hf = 4 mhz, c l,eff = 16 pf 450 ? hfxtbypass = 0, hfxtdrive = 1, hffreq = 1 f hfxt,hf = 8 mhz, c l,eff = 16 pf 320 hfxtbypass = 0, hfxtdrive = 2, hffreq = 2 f hfxt,hf = 16 mhz, c l,eff = 16 pf 200 hfxtbypass = 0, hfxtdrive = 3, hffreq = 3 f hfxt,hf = 24 mhz, c l,eff = 16 pf 200 t start,hfxt startup time (6) f osc = 4 mhz, hfxtbypass = 0, hfxtdrive = 0, hffreq = 1, t a = 25 c, c l,eff = 16 pf 3.0 v 1.6 ms f osc = 24 mhz, hfxtbypass = 0, hfxtdrive = 3, hffreq = 3, t a = 25 c, c l,eff = 16 pf 0.6 c hfxin integrated load capacitance at hfxin terminai (7) (8) 2 pf c hfxout integrated load capacitance at hfxout terminai (7) (8) 2 pf f fault,hfxt oscillator fault frequency (9) (10) 0 800 khz
39 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated the dco (see table 5-6 ) is an internal digitally controlled oscillator (dco) with selectable frequencies. (1) calculated using the box method: (max( ? 40 c to 85 o c) - min( ? 40 c to 85 o c)) / min( ? 40 c to 85 o c) / (85 o c - (-40 o c)) table 5-6. dco over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit f dco1 dco frequency range 1 mhz, trimmed measured at smclk, divide by 1, dcorsel = 0, dcofsel = 0, dcorsel = 1, dcofsel = 0 1 3.5% mhz f dco2.7 dco frequency range 2.7 mhz, trimmed measured at smclk, divide by 1, dcorsel = 0, dcofsel = 1 2.667 3.5% mhz f dco3.5 dco frequency range 3.5 mhz, trimmed measured at smclk, divide by 1, dcorsel = 0, dcofsel = 2 3.5 3.5% mhz f dco4 dco frequency range 4 mhz, trimmed measured at smclk, divide by 1 dcorsel = 0, dcofsel = 3 4 3.5% mhz f dco5.3 dco frequency range 5.3 mhz, trimmed measured at smclk, divide by 1, dcorsel = 0, dcofsel = 4, dcorsel = 1, dcofsel = 1 5.333 3.5% mhz f dco7 dco frequency range 7 mhz, trimmed measured at smclk, divide by 1, dcorsel = 0, dcofsel = 5, dcorsel = 1, dcofsel = 2 7 3.5% mhz f dco8 dco frequency range 8 mhz, trimmed measured at smclk, divide by 1, dcorsel = 0, dcofsel = 6, dcorsel = 1, dcofsel = 3 8 3.5% mhz f dco16 dco frequency range 16 mhz, trimmed measured at smclk, divide by 1, dcorsel = 1, dcofsel = 4 16 3.5% mhz f dco21 dco frequency range 21 mhz, trimmed measured at smclk, divide by 2, dcorsel = 1, dcofsel = 5 21 3.5% mhz f dco24 dco frequency range 24 mhz, trimmed measured at smclk, divide by 2, dcorsel = 1, dcofsel = 6 24 3.5% mhz f dco,dc duty cycle measured at smclk, divide by 1, no external divide, all dcorsel and dcofsel settings except dcorsel = 1 with dcofsel = 5, and dcorsel = 1 with dcofsel = 6 48% 50% 52% t dco, jitter dco jitter based on f signal = 10 khz and dco used for 12-bit sar adc sampling source. this achieves greather than 74-db snr due to jitter (that is, limited by adc performance). 2 3 ns df dco /dt dco temperature drift (1) 3.0 v 0.01 %/ o c
40 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated the vlo (see table 5-7 ) is an internal very-low-power low-frequency oscillator with 10-khz typical frequency. (1) vlo frequency may decrease in lpm3 or lpm4 mode. the typical ratio of vlo freuqencies (lpm3/4 to am) is 85%. (2) calculated using the box method: (max( ? 40 c to 85 c) ? min( ? 40 c to 85 c)) / min( ? 40 c to 85 c) / (85 c ? ( ? 40 c)) (3) calculated using the box method: (max(1.8 to 3.6 v) ? min(1.8 to 3.6 v)) / min(1.8 to 3.6 v) / (3.6 v ? 1.8 v) table 5-7. internal very-low-power low-frequency oscillator (vlo) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit i vlo current consumption 100 na f vlo vlo frequency (1) measured at aclk 6 9.4 14 khz df vlo /d t vlo frequency temperature drift measured at aclk (2) 0.2 %/ c df vlo /dv cc vlo frequency supply voltage drift measured at aclk (3) 0.7 %/v f vlo,dc duty cycle measured at aclk 40% 50% 60% the module oscillator (modosc) is an internal low-power oscillator with 5-mhz typical frequency (see table 5-8 ). (1) calculated using the box method: (max( ? 40 c to 85 c) ? min( ? 40 c to 85 c)) / min( ? 40 c to 85 c) / (85 c ? ( ? 40 c)) (2) calculated using the box method: (max(1.8 v to 3.6 v) ? min(1.8 v to 3.6 v)) / min(1.8 v to 3.6 v) / (3.6 v ? 1.8 v) table 5-8. module oscillator (modosc) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit i modosc current consumption enabled 25 a f modosc modosc frequency 4.0 4.8 5.4 mhz f modosc /dt modosc frequency temperature drift (1) 0.08 %/ f modosc /dv cc modosc frequency supply voltage drift (2) 1.4 %/v dc modosc duty cycle measured at smclk, divide by 1 40% 50% 60%
41 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated 5.12.4 wake-up characteristics table 5-9 lists the wake-up times. (1) the wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first externally observable mclk clock edge with mclkreqen = 1. this time includes the activation of the fram during wake up. with mclkreqen = 0, the externally observable mclk clock is gated one additional cycle. (2) the wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first instruction of the user program is executed. table 5-9. wake-up times from low-power modes and reset over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see figure 5-6 and figure 5-7 ) parameter test conditions v cc min typ max unit t wake-up fram (additional) wake-up time to activate the fram in am if previously disabled by the fram controller or from an lpm if immediate activation is selected for wakeup 6 10 s t wake-up lpm0 wake-up time from lpm0 to active mode (1) 2.2 v, 3.0 v 400 ns + 1.5 / f dco t wake-up lpm1 wake-up time from lpm1 to active mode (1) 2.2 v, 3.0 v 6 s t wake-up lpm2 wake-up time from lpm2 to active mode (1) 2.2 v, 3.0 v 6 s t wake-up lpm3 wake-up time from lpm3 to active mode (1) 2.2 v, 3.0 v 6.6 + 2.0 / f dco 9.6 + 2.5 / f dco s t wake-up lpm4 wake-up time from lpm4 to active mode (1) 2.2 v, 3.0 v 6.6 + 2.0 / f dco 9.6 + 2.5 / f dco s t wake-up lpm3.5 wake-up time from lpm3.5 to active mode (2) 2.2 v, 3.0 v 250 350 s t wake-up lpm4.5 wake-up time from lpm4.5 to active mode (2) svshe = 1 2.2 v, 3.0 v 250 350 s svshe = 0 2.2 v, 3.0 v 0.4 0.8 ms t wake-up-rst wake-up time from a rst pin triggered reset to active mode (2) 2.2 v, 3.0 v 300 403 s t wake-up-bor wake-up time from power-up to active mode (2) 2.2 v, 3.0 v 0.5 1 ms 5.12.4.1 typical characteristics, average lpm currents vs wake-up frequency note: the average wake-up current does not include the energy required in active mode; for example, for an interrupt service routine (isr) or to reconfigure the device. figure 5-6. average lpm currents vs wake-up frequency at 25 c wake-up frequency (hz) average wake-up current (a) 0.001 0.01 0.1 1 10 100 1000 10000 100000 0.1 1 10 100 1000 5000 lpm0 lpm1 lpm2,xt12 lpm3,xt12 lpm3.5,xt12
42 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated note: the average wake-up current does not include the energy required in active mode; for example, for an isr or to reconfigure the device. figure 5-7. average lpm currents vs wake-up frequency at 85 c table 5-10 lists the typical charge required to wake up from lpm or reset. (1) charge used during the wake-up time from a given low-power mode to active mode. this does not include the energy required in active mode (for example, for an isr). (2) charge required until start of user code. this does not include the energy required to reconfigure the device. table 5-10. typical wake-up charge (1) parameter test conditions min typ max unit q wake-up fram charge used for activating the fram in am or during wake-up from lpm0 if previously disabled by the fram controller. 16.5 nas q wake-up lpm0 charge used for wake-up from lpm0 to active mode (with fram active) 3.8 nas q wake-up lpm1 charge used for wake-up from lpm1 to active mode (with fram active) 21 nas q wake-up lpm2 charge used for wake-up from lpm2 to active mode (with fram active) 22 nas q wake-up lpm3 charge used for wake-up from lpm3 to active mode (with fram active) 25 nas q wake-up lpm4 charge used for wake-up from lpm4 to active mode (with fram active) 25 nas q wake-up lpm3.5 charge used for wake-up from lpm3.5 to active mode (2) 121 nas q wake-up lpm4.5 charge used for wake-up from lpm4.5 to active mode (2) svshe = 1 123 nas svshe = 0 121 q wake-up-reset charge used for reset from rst or bor event to active mode (2) 102 nas wake-up frequency (hz) average wake-up current (a) 0.001 0.01 0.1 1 10 100 1000 10000 100000 0.1 1 10 100 1000 5000 lpm0 lpm1 lpm2,xt12 lpm3,xt12 lpm3.5,xt12
43 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated 5.12.5 digital i/os table 5-11 lists the characteristics of the digital inputs. (1) if the port pins pj.4/lfxin and pj.5/lfxout are used as digital i/os, they are connected by a 4-pf capacitor and a 35-m ? resistor in series. at frequencies of approximately 1 khz and lower, the 4-pf capacitor can add to the pin capacitance of pj.4/lfxin and/or pj.5/lfxout. (2) the input leakage current is measured with v ss or v cc applied to the corresponding pins, unless otherwise noted. (3) the input leakage of the digital port pins is measured individually. the port pin is selected for input and the pullup or pulldown resistor is disabled. (4) an external signal sets the interrupt flag every time the minimum interrupt pulse duration t (int) is met. it may be set by trigger signals shorter than t (int) . (5) not applicable if rst/nmi pin configured as nmi . table 5-11. digital inputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit v it+ positive-going input threshold voltage 2.2 v 1.2 1.65 v 3.0 v 1.65 2.25 v it ? negative-going input threshold voltage 2.2 v 0.55 1.00 v 3.0 v 0.75 1.35 v hys input voltage hysteresis (v it+ ? v it ? ) 2.2 v 0.44 0.98 v 3.0 v 0.60 1.30 r pull pullup or pulldown resistor for pullup: v in = v ss , for pulldown: v in = v cc 20 35 50 k c i,dig input capacitance, digital only port pins v in = v ss or v cc 3 pf c i,ana input capacitance, port pins with shared analog functions (1) v in = v ss or v cc 5 pf i lkg(px.y) high-impedance input leakage current see (2) (3) 2.2 v, 3.0 v ? 20 +20 na t (int) external interrupt timing (external trigger pulse duration to set interrupt flag) (4) ports with interrupt capability (see section 1.4 and table 4-2 ) 2.2 v, 3.0 v 20 ns t (rst) external reset pulse duration on rst (5) 2.2 v, 3.0 v 2 s
44 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated table 5-12 lists the characteristics of the digital outputs. (1) the maximum total current, i (ohmax) and i (olmax) , for all outputs combined should not exceed 48 ma to hold the maximum voltage drop specified. (2) the maximum total current, i (ohmax) and i (olmax) , for all outputs combined should not exceed 100 ma to hold the maximum voltage drop specified. (3) the port can output frequencies at least up to the specified limit, and it might support higher frequencies. (4) a resistive divider with 2 r1 and r1 = 1.6 k between v cc and v ss is used as load. the output is connected to the center tap of the divider. c l = 20 pf is connected from the output to v ss . (5) the output voltage reaches at least 10% and 90% v cc at the specified toggle frequency. table 5-12. digital outputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit v oh high-level output voltage (see figure 5-10 and figure 5-11 ) i (ohmax) = ? 1 ma (1) 2.2 v v cc ? 0.25 v cc v i (ohmax) = ? 3 ma (2) v cc ? 0.60 v cc i (ohmax) = ? 2 ma (1) 3.0 v v cc ? 0.25 v cc i (ohmax) = ? 6 ma (2) v cc ? 0.60 v cc v ol low-level output voltage (see figure 5-8 and figure 5-9 ) i (olmax) = 1 ma (1) 2.2 v v ss v ss + 0.25 v i (olmax) = 3 ma (2) v ss v ss + 0.60 i (olmax) = 2 ma (1) 3.0 v v ss v ss + 0.25 i (olmax) = 6 ma (2) v ss v ss + 0.60 f px.y port output frequency (with load) (3) c l = 20 pf, r l (4) (5) 2.2 v 16 mhz 3.0 v 16 f port_clk clock output frequency (3) aclk, mclk, or smclk at configured output port, c l = 20 pf (5) 2.2 v 16 mhz 3.0 v 16 t rise,dig port output rise time, digital only port pins c l = 20 pf 2.2 v 4 15 ns 3.0 v 3 15 t fall,dig port output fall time, digital only port pins c l = 20 pf 2.2 v 4 15 ns 3.0 v 3 15 t rise,ana port output rise time, port pins with shared analog functions c l = 20 pf 2.2 v 6 15 ns 3.0 v 4 15 t fall,ana port output fall time, port pins with shared analog functions c l = 20 pf 2.2 v 6 15 ns 3.0 v 4 15
45 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated 5.12.5.1 typical characteristics, digital outputs at 3.0 v and 2.2 v v cc = 2.2 v figure 5-8. typical low-level output current vs low-level output voltage v cc = 3.0 v figure 5-9. typical low-level output current vs low-level output voltage v cc = 2.2 v figure 5-10. typical high-level output current vs high-level output voltage v cc = 3.0 v figure 5-11. typical high-level output current vs high-level output voltage 0 5 10 15 0 0.5 1 1.5 2 low-level output current (ma) low-level output voltage (v) 25c 85c c001 p1.1 0 10 20 30 0 0.5 1 1.5 2 2.5 3 low-level output current (ma) low-level output voltage (v) 25c 85c c001 p1.1 -15 -10 -5 0 0 0.5 1 1.5 2 high-level output current (ma) high-level output voltage (v) 25c 85c c001 p1.1 -30 -20 -10 0 0 0.5 1 1.5 2 2.5 3 high-level output current (ma) high-level output voltage (v) 25c 85c c001 p1.1
46 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated table 5-13 lists the supported oscillation frequencies on the digital i/os. (1) c l is the external load capacitance connected from the output to v ss and includes all parasitic effects such as pcb traces. table 5-13. pin-oscillator frequency, ports px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit fo px.y pin-oscillator frequency (see figure 5-12 and figure 5-13 ) px.y, c l = 10 pf (1) 3.0 v 1200 khz px.y, c l = 20 pf (1) 3.0 v 650 khz 5.12.5.2 typical characteristics, pin-oscillator frequency v cc = 2.2 v one output active at a time. figure 5-12. typical oscillation frequency vs load capacitance v cc = 3.0 v one output active at a time. figure 5-13. typical oscillation frequency vs load capacitance c l , load capacitance (pf) pin oscillator frequency (khz) 10 20 30 40 50 60 70 80 100 200 100 200 300 400 500 600 700 800 1000 2000 best fit 25c 85c c l , load capacitance (pf) pin oscillator frequency (khz) 10 20 30 40 50 60 70 80 100 200 100 200 300 400 500 600 700 800 1000 2000 best fit 25c 85c
47 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated 5.12.6 lea (low-energy accelerator) (msp430fr599x only) the lea module is a hardware engine designed for operations that involve vector-based signal processing. table 5-14 lists the performance characteristics of the lea module. table 5-14. low energy accelerator performance over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit f lea frequency for specified performance mclk 16 mhz w_lea_fft lea subsystem energy on fast fourier transform complex fft 128-point q.15 with random data in lea-ram v core = 3 v, mclk = 16 mhz 350 nj w_lea_fir lea subsystem energy on finite impulse response real fir on random q.31 data with 128 taps on 24 points v core = 3 v, mclk = 16 mhz 2.6 j w_lea_add lea subsystem energy on additions on 32 q.31 elements with random value out of lea-ram with linear address increment v core = 3 v, mclk = 16 mhz 6.6 nj 5.12.7 timer_a and timer_b timer_a and timer_b are 16-bit timers and counters with multiple capture/compare registers. table 5-15 lists the timer_a characteristics, and table 5-16 lists the timer_b characteristics. table 5-15. timer_a over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min max unit f ta timer_a input clock frequency internal: smclk or aclk, external: taclk, duty cycle = 50% 10% 2.2 v, 3.0 v 16 mhz t ta,cap timer_a capture timing all capture inputs, minimum pulse duration required for capture 2.2 v, 3.0 v 20 ns table 5-16. timer_b over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min max unit f tb timer_b input clock frequency internal: smclk or aclk, external: tbclk, duty cycle = 50% 10% 2.2 v, 3.0 v 16 mhz t tb,cap timer_b capture timing all capture inputs, minimum pulse duration required for capture 2.2 v, 3.0 v 20 ns
48 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated 5.12.8 eusci the enhanced universal serial communication interface (eusci) supports multiple serial communication modes with one hardware module. the eusci_a module supports uart and spi modes. the eusci_b module supports i 2 c and spi modes. table 5-17 lists the uart clock frequencies. table 5-17. eusci (uart mode) clock frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min max unit f eusci eusci input clock frequency internal: smclk or aclk, external: uclk, duty cycle = 50% 10% 16 mhz f bitclk bitclk clock frequency (equals baud rate in mbaud) 4 mhz table 5-18 lists the uart operating characteristics. (1) pulses on the uart receive input (ucxrx) shorter than the uart receive deglitch time are suppressed. thus the selected deglitch time can limit the maximum useable baud rate. to ensure that pulses are correctly recognized, their duration should exceed the maximum specification of the deglitch time. table 5-18. eusci (uart mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min max unit t t uart receive deglitch time (1) ucglitx = 0 2.2 v, 3.0 v 5 30 ns ucglitx = 1 20 90 ucglitx = 2 35 160 ucglitx = 3 50 220
49 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated table 5-19 lists the spi master mode clock frequencies. table 5-19. eusci (spi master mode) clock frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min max unit f eusci eusci input clock frequency internal: smclk or aclk, duty cycle = 50% 10% 16 mhz table 5-20 lists the spi master mode operating characteristics. (1) f ucxclk = 1/2 t lo/hi with t lo/hi = max(t valid,mo(eusci) + t su,si(slave) , t su,mi(eusci) + t valid,so(slave) ) for the slave parameters t su,si(slave) and t valid,so(slave) , see the spi parameters of the attached slave. (2) specifies the time to drive the next valid data to the simo output after the output changing uclk clock edge. see the timing diagrams in figure 5-14 and figure 5-15 . (3) specifies how long data on the simo output is valid after the output changing uclk clock edge. negative values indicate that the data on the simo output can become invalid before the output changing clock edge observed on uclk. see the timing diagrams in figure 5- 14 and figure 5-15 . table 5-20. eusci (spi master mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) parameter test conditions v cc min typ max unit t ste,lead ste lead time, ste active to clock ucstem = 1, ucmodex = 01 or 10 1 ucxclk cycles t ste,lag ste lag time, last clock to ste inactive ucstem = 1, ucmodex = 01 or 10 1 t ste,acc ste access time, ste active to simo data out ucstem = 0, ucmodex = 01 or 10 2.2 v, 3.0 v 60 ns t ste,dis ste disable time, ste inactive to somi high impedance ucstem = 0, ucmodex = 01 or 10 2.2 v, 3.0 v 80 ns t su,mi somi input data setup time 2.2 v 40 ns 3.0 v 40 t hd,mi somi input data hold time 2.2 v 0 ns 3.0 v 0 t valid,mo simo output data valid time (2) uclk edge to simo valid, c l = 20 pf 2.2 v 11 ns 3.0 v 10 t hd,mo simo output data hold time (3) c l = 20 pf 2.2 v 0 ns 3.0 v 0
50 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated figure 5-14. spi master mode, ckph = 0 figure 5-15. spi master mode, ckph = 1 t su,mi t hd,mi uclk somisimo t valid,mo ckpl = 0 ckpl = 1 t low/high t low/high 1/f ucxclk t ste,lead t ste,lag t ste,acc ucmodex = 01ucmodex = 10 ste t hd,mo t ste,dis t su,mi t hd,mi uclk somisimo t valid,mo ckpl = 0 ckpl = 1 t low/high t low/high 1/f ucxclk ste t ste,lead t ste,lag ucmodex = 01ucmodex = 10 t hd,mo t ste,acc t ste,dis
51 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated table 5-21 lists the spi slave mode operating characteristics. (1) f ucxclk = 1/2 t lo/hi with t lo/hi max(t valid,mo(master) + t su,si(eusci) , t su,mi(master) + t valid,so(eusci) ) for the master parameters t su,mi(master) and t valid,mo(master) , see the spi parameters of the attached master. (2) specifies the time to drive the next valid data to the somi output after the output changing uclk clock edge. see the timing diagrams in figure 5-16 and figure 5-17 . (3) specifies how long data on the somi output is valid after the output changing uclk clock edge. see the timing diagrams in figure 5-16 and figure 5-17 . table 5-21. eusci (spi slave mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) parameter test conditions v cc min max unit t ste,lead ste lead time, ste active to clock 2.2 v 45 ns 3.0 v 40 t ste,lag ste lag time, last clock to ste inactive 2.2 v 2 ns 3.0 v 3 t ste,acc ste access time, ste active to somi data out 2.2 v 45 ns 3.0 v 40 t ste,dis ste disable time, ste inactive to somi high impedance 2.2 v 50 ns 3.0 v 45 t su,si simo input data setup time 2.2 v 4 ns 3.0 v 4 t hd,si simo input data hold time 2.2 v 7 ns 3.0 v 7 t valid,so somi output data valid time (2) uclk edge to somi valid, c l = 20 pf 2.2 v 35 ns 3.0 v 35 t hd,so somi output data hold time (3) c l = 20 pf 2.2 v 0 ns 3.0 v 0
52 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated figure 5-16. spi slave mode, ckph = 0 figure 5-17. spi slave mode, ckph = 1 uclk ckpl = 0 ckpl = 1 somi simo t su,si t hd,si t valid,so t hd,so t low/high 1/f ucxclk t low/high t ste,dis t ste,acc ste t ste,lead t ste,lag ucmodex = 01ucmodex = 10 uclk ckpl = 0 ckpl = 1 somi simo t su,si t hd,si t valid,so t low/high 1/f ucxclk t low/high t ste,dis t ste,acc ste t ste,lead t ste,lag ucmodex = 01ucmodex = 10 t hd,so
53 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated table 5-22 lists the i 2 c mode operating characteristics. table 5-22. eusci (i 2 c mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see figure 5-18 ) parameter test conditions v cc min typ max unit f eusci eusci input clock frequency internal: smclk or aclk, external: uclk, duty cycle = 50% 10% 16 mhz f scl scl clock frequency 2.2 v, 3.0 v 0 400 khz t hd,sta hold time (repeated) start f scl = 100 khz 2.2 v, 3.0 v 4.0 s f scl > 100 khz 0.6 t su,sta setup time for a repeated start f scl = 100 khz 2.2 v, 3.0 v 4.7 s f scl > 100 khz 0.6 t hd,dat data hold time 2.2 v, 3.0 v 0 ns t su,dat data setup time 2.2 v, 3.0 v 100 ns t su,sto setup time for stop f scl = 100 khz 2.2 v, 3.0 v 4.0 s f scl > 100 khz 0.6 t sp pulse duration of spikes suppressed by input filter ucglitx = 0 2.2 v, 3.0 v 50 250 ns ucglitx = 1 25 125 ucglitx = 2 12.5 62.5 ucglitx = 3 6.3 31.5 t timeout clock low time-out uccltox = 1 2.2 v, 3.0 v 27 ms uccltox = 2 30 uccltox = 3 33 figure 5-18. i 2 c mode timing sda scl t hd,dat t su,dat t hd,sta t high t low t buf t hd,sta t su,sta t sp t su,sto
54 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated 5.12.9 adc12_b the adc12_b module supports fast 12-bit analog-to-digital conversions. the module implements a 12-bit sar core, sample select control, and up to 32 independent conversion-and-control buffers. the conversion-and-control buffer allows up to 32 independent analog-to-digital converter (adc) samples to be converted and stored without any cpu intervention. table 5-23 lists the power supply and input range conditions. (1) the analog input voltage range must be within the selected reference voltage range v r+ to v r ? for valid conversion results. (2) the internal reference supply current is not included in current consumption parameter i (adc12_b) . (3) approximately 60% (typical) of the total current into the avcc and dvcc terminals is from avcc. table 5-23. 12-bit adc, power supply and input range conditions over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min nom max unit v (ax) analog input voltage range (1) all adc12 analog input pins ax 0 avcc v i (adc12_b) single-ended mode operating supply current into avcc plus dvcc terminals (2) (3) f adc12clk = modclk, adc12on = 1, adc12pwrmd = 0, adc12dif = 0, refon = 0, adc12shtx = 0, adc12div = 0 3.0 v 145 199 a 2.2 v 140 190 i (adc12_b) differential mode operating supply current into avcc plus dvcc terminals (2) (3) f adc12clk = modclk, adc12on = 1, adc12pwrmd = 0, adc12dif = 1, refon = 0, adc12shtx= 0, adc12div = 0 3.0 v 175 245 a 2.2 v 170 230 i (adc12_b) single-ended low-power mode operating supply current into avcc plus dvcc terminals (2) (3) f adc12clk = modclk / 4, adc12on = 1, adc12pwrmd = 1, adc12dif = 0, refon = 0, adc12shtx = 0, adc12div = 0 3.0 v 85 125 a 2.2 v 83 120 i (adc12_b) differential low- power mode operating supply current into avcc plus dvcc terminals (2) (3) f adc12clk = modclk / 4, adc12on = 1, adc12pwrmd = 1, adc12dif = 1, refon = 0, adc12shtx= 0, adc12div = 0 3.0 v 110 165 a 2.2 v 109 160 c i input capacitance only one terminal ax can be selected at one time 2.2 v 10 15 pf r i input mux on-resistance 0 v v (ax) av cc > 2 v 0.5 4 k < 2 v 1 10
55 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated table 5-24 lists the timing parameters. (1) the adc12osc is sourced directly from modosc inside the ucs. (2) 14 1 / f adc12clk . if adc12winc = 1 then 15 1 / f adc12clk (3) the condition is that the error in a conversion started after t adc12on is less than 0.5 lsb. the reference and input signal are already settled. (4) approximately ten tau ( ) are needed to get an error of less than 0.5 lsb: t sample = ln(2 n+2 ) x (r s + r i ) x (c i + c pext ), where n = adc resolution = 12, r s = external source resistance, c pext = external parasitic capacitance. (5) 6 1 / f adc12clk table 5-24. 12-bit adc, timing parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit f adc12clk frequency for specified performance for specified performance of adc12 linearity parameters with adc12pwrmd = 0. if adc12pwrmd = 1, the maximum is 1/4 of the value shown here. 0.45 5.4 mhz f adc12clk frequency for reduced performance linearity parameters have reduced performance 32.768 khz f adc12osc internal oscillator (1) adc12div = 0, f adc12clk = f adc12osc from modclk 4 4.8 5.4 mhz t convert conversion time refon = 0, internal oscillator, f adc12clk = f adc12osc from modclk, adc12winc = 0 2.6 3.5 s external f adc12clk from aclk, mclk, or smclk, adc12ssel 0 (2) t adc12on turnon settling time of the adc see (3) 100 ns t adc12off time adc must be off before it can be turned on again t adc12off must be met to make sure that t adc12on time holds 100 ns t sample sampling time r s = 400 , r i = 4 k , c i = 15 pf, c pext = 8 pf (4) all pulse sample mode (adc12shp = 1) and extended sample mode (adc12shp = 0) with buffered reference (adc12vrsel = 0x1, 0x3, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf) 1 s extended sample mode (adc12shp = 0) with unbuffered reference (adc12vrsel = 0x0, 0x2, 0x4, 0x6, 0xc, 0xe) (5)
56 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated table 5-25 lists the linearity parameters. (1) offset is measured as the input voltage (at which adc output transitions from 0 to 1) minus 0.5 lsb. (2) offset increases as i r drop increases when v r ? is avss. (3) for details, see the device descriptor table section in the msp430fr58xx, msp430fr59xx, msp430fr68xx, and msp430fr69xx family user ' s guide . table 5-25. 12-bit adc, linearity parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit e i integral linearity error (inl) for differential input with external voltage reference (adc12vrsel = 0x2, 0x3, 0x4, 0x14, 0x15), 1.2 v (v r+ ? v r ? ) av cc 1.8 lsb integral linearity error (inl) for single-ended inputs 2.2 e d differential linearity error (dnl) with external voltage reference (adc12vrsel = 0x2, 0x3, 0x4, 0x14, 0x15) ? 0.99 +1.0 lsb e o offset error (1) (2) adc12vrsel = 0x1 without tlv calibration, tlv calibration data can be used to improve the parameter (3) 0.5 1.5 mv e g gain error with internal voltage reference vref = 2.5 v (adc12vrsel = 0x1, 0x7, 0x9, 0xb, or 0xd) 0.2% 1.7% with internal voltage reference vref = 1.2 v (adc12vrsel = 0x1, 0x7, 0x9, 0xb, or 0xd) 0.2% 2.5% with external voltage reference without internal buffer (adc12vrsel = 0x2 or 0x4) without tlv calibration, v r+ = 2.5 v, v r ? = avss 1 3 lsb with external voltage reference with internal buffer (adc12vrsel = 0x3), v r+ = 2.5 v, v r ? = avss 2 27 e t total unadjusted error with internal voltage reference vref = 2.5 v (adc12vrsel = 0x1, 0x7, 0x9, 0xb, or 0xd) 0.2% 1.8 % with internal voltage reference vref = 1.2 v (adc12vrsel = 0x1, 0x7, 0x9, 0xb, or 0xd) 0.2% 2.6% with external voltage reference without internal buffer (adc12vrsel = 0x2 or 0x4) without tlv calibration, v r+ = 2.5 v, v r ? = avss 1 5 lsb with external voltage reference with internal buffer (adc12vrsel = 0x3), v r+ = 2.5 v, v r ? = avss 1 28
57 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated table 5-26 lists the dynamic performance characteristics when using an external reference. (1) enob = (sinad ? 1.76) / 6.02 table 5-26. 12-bit adc, dynamic performance with external reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit resolution number of no missing code output-code bits 12 bits snr signal-to-noise with differential inputs v r+ = 2.5 v, v r ? = av ss 71 db signal-to-noise with single-ended inputs v r+ = 2.5 v, v r ? = av ss 70 enob effective number of bits with differential inputs (1) v r+ = 2.5 v, v r ? = av ss 11.4 bits effective number of bits with single-ended inputs (1) v r+ = 2.5 v, v r ? = av ss 11.1 effective number of bits with 32.768-khz clock (reduced performance) (1) reduced performance with f adc12clk from aclk lfxt 32.768 khz, v r+ = 2.5 v, v r ? = av ss 10.9 table 5-27 lists the dynamic performance characteristics when using an internal reference. (1) enob = (sinad ? 1.76) / 6.02 table 5-27. 12-bit adc, dynamic performance with internal reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit resolution number of no missing code output code bits 12 bits snr signal-to-noise with differential inputs v r+ = 2.5 v, v r ? = av ss 70 db signal-to-noise with single-ended inputs v r+ = 2.5 v, v r ? = av ss 69 enob effective number of bits with differential inputs (1) v r+ = 2.5 v, v r ? = av ss 11.4 bits effective number of bits with single-ended inputs (1) v r+ = 2.5 v, v r ? = av ss 11.0 effective number of bits with 32.768-khz clock (reduced performance) (1) reduced performance with f adc12clk from aclk lfxt 32.768 khz, v r+ = 2.5 v, v r ? = av ss 10.9
58 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated table 5-28 lists the temperature sensor and built-in v1/2 characteristics. (1) the temperature sensor offset can be as much as 30 c. ti recommends a single-point calibration to minimize the offset error of the built-in temperature sensor. (2) the device descriptor structure contains calibration values for 30 c 3 c and 85 c 3 c for each of the available reference voltage levels. the sensor voltage can be computed as v sense = tc sensor (temperature, c) + v sensor , where tc sensor and v sensor can be computed from the calibration values for higher accuracy. (3) the typical equivalent impedance of the sensor is 250 k . the sample time required includes the sensor on time (t sensor(on) ). (4) the on time (t v1/2(on) ) is included in the sampling time (t v1/2(sample) ); no additional on time is needed. table 5-28. 12-bit adc, temperature sensor and built-in v 1/2 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit v sensor temperature sensor voltage (1) (2) (see figure 5-19 ) adc12on = 1, adc12tcmap = 1, t a = 0 c 700 mv tc sensor see (2) adc12on = 1, adc12tcmap = 1 2.5 mv/ c t sensor(sample) sample time required if adctcmap = 1 and channel (max ? 1) is selected (3) adc12on = 1, adc12tcmap = 1, error of conversion result 1 lsb 30 s v 1/2 avcc voltage divider for adc12batmap = 1 on max input channel adc12on = 1, adc12batmap = 1 47.5% 50% 52.5% i v 1/2 current for battery monitor during sample time adc12on = 1, adc12batmap = 1 38 72 a t v 1/2 (sample) sample time required if adc12batmap = 1 and channel max is selected (4) adc12on = 1, adc12batmap = 1 1.7 s figure 5-19. typical temperature sensor voltage 500 550 600 650 700 750 800 850 900 950 C40 C20 0 20 40 60 80 typical temperature sensor voltage (mv) ambient temperature (c)
59 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated table 5-29 lists the external reference characteristics. (1) the external reference is used during adc conversion to charge and discharge the capacitance array. the input capacitance, c i , is also the dynamic load for an external reference during conversion. the dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy. (2) two decoupling capacitors, 10 f and 470 nf, should be connected to veref to decouple the dynamic current required for an external reference source if it is used for the adc12_b. also see the msp430fr58xx, msp430fr59xx, msp430fr68xx, and msp430fr69xx family user ' s guide . table 5-29. 12-bit adc, external reference (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min max unit v r+ positive external reference voltage input veref+ or veref- based on adc12vrsel bit v r+ > v r ? 1.2 av cc v v r ? negative external reference voltage input veref+ or veref- based on adc12vrsel bit v r+ > v r ? 0 1.2 v v r+ ? v r ? differential external reference voltage input v r+ > v r ? 1.2 av cc v i veref+ , i veref- static input current singled-ended input mode 1.2 v v eref+ v avcc , v eref- = 0 v f adc12clk = 5 mhz, adc12shtx = 1h, adc12dif = 0, adc12pwrmd = 0 10 a 1.2 v v eref+ v avcc , v eref- = 0 v f adc12clk = 5 mhz, adc12shtx = 8h, adc12dif = 0, adc12pwrmd = 01 2.5 i veref+ , i veref- static input current differential input mode 1.2 v v eref+ v avcc , v eref- = 0 v f adc12clk = 5 mhz, adc12shtx = 1h, adc12dif = 1, , adc12pwrmd = 0 20 a 1.2 v v eref+ v avcc , v eref- = 0 v f adc12clk = 5 mhz, adc12shtx = 8h, adc12dif = 1, , adc12pwrmd = 1 5 i veref+ peak input current with single-ended input 0 v v eref+ v avcc , adc12dif = 0 1.5 ma i veref+ peak input current with differential input 0 v v eref+ v avcc , adc12dif = 1 3 ma c veref+/- capacitance at veref+ or veref- terminal see (2) 10 f
60 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated 5.12.10 reference the reference module (ref) generates all of the critical reference voltages that can be used by various analog peripherals in a given device. the heart of the reference system is the bandgap from which all other references are derived by unity or noninverting gain stages. the refgen subsystem consists of the bandgap, the bandgap bias, and the noninverting buffer stage, which generates the three primary voltage reference available in the system (1.2 v, 2.0 v, and 2.5 v). table 5-30 lists the operating characteristics of the built-in reference. (1) internal reference noise affects adc performance when adc uses internal reference. see designing with the msp430fr59xx and msp430fr58xx adc for details on optimizing adc performance for your application with the choice of internal or external reference. (2) buffer offset affects adc gain error and thus total unadjusted error. (3) buffer offset affects adc gain error and thus total unadjusted error. (4) the internal reference current is supplied through the avcc terminal. (5) calculated using the box method: (max( ? 40 c to 85 c) ? min( ? 40 c to 85 c)) / min( ? 40 c to 85 c)/(85 c ? ( ? 40 c)). table 5-30. ref, built-in reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit v ref+ positive built-in reference voltage output refvsel = {2} for 2.5 v, refon = 1 2.7 v 2.5 1.5% v refvsel = {1} for 2.0 v, refon = 1 2.2 v 2.0 1.5% refvsel = {0} for 1.2 v, refon = 1 1.8 v 1.2 1.8% noise rms noise at vref (1) from 0.1 hz to 10 hz, refvsel = {0} 30 130 v v os_buf_int vref adc buf_int buffer offset (2) t a = 25 c , adc on, refvsel = {0}, refon = 1, refout = 0 ? 16 +16 mv v os_buf_ext vref adc buf_ext buffer offset (3) t a = 25 c, refvsel = {0} , refout = 1, refon = 1 or adc on ? 16 +16 mv av cc(min) avcc minimum voltage, positive built-in reference active refvsel = {0} for 1.2 v 1.8 v refvsel = {1} for 2.0 v 2.2 refvsel = {2} for 2.5 v 2.7 i ref+ operating supply current into avcc terminal (4) refon = 1 3 v 19 26 a i ref+_adc_buf operating supply current into avcc terminal (4) adc on, refout = 0, refvsel = {0, 1, 2}, adc12pwrmd = 0, 3 v 247 400 a adc on, refout = 1, refvsel = {0, 1, 2}, adc12pwrmd = 0 1053 1820 adc on, refout = 0, refvsel = {0, 1, 2}, adc12pwrmd = 1 153 240 adc on, refout = 1, refvsel = {0, 1, 2}, adc12pwrmd = 1 581 1030 adc off, refon = 1, refout = 1, refvsel = {0, 1, 2} 1105 1890 i o(vref+) vref maximum load current, vref+ terminal refvsel = {0, 1, 2}, av cc = av cc(min) for each reference level, refon = refout = 1 ? 1000 10 a vout/ io(vref+) load-current regulation, vref+ terminal refvsel = {0, 1, 2}, i o(vref+) = +10 a or ? 1000 a av cc = av cc(min) for each reference level, refon = refout = 1 1500 v/ma c vref+/- capacitance at vref+ and vref- terminals refon = refout = 1 0 100 pf tc ref+ temperature coefficient of built-in reference refvsel = {0, 1, 2}, refon = refout = 1, t a = ? 40 c to 85 c (5) 24 50 ppm/k psrr_dc power supply rejection ratio (dc) av cc = av cc(min) to av cc(max) , t a = 25 c, refvsel = {0, 1, 2}, refon = refout = 1 100 400 v/v psrr_ac power supply rejection ratio (ac) dav cc = 0.1 v at 1 khz 3.0 mv/v
61 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated table 5-30. ref, built-in reference (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit (6) the condition is that the error in a conversion started after t refon is less than 0.5 lsb. t settle settling time of reference voltage (6) av cc = av cc(min) to av cc(max) , refvsel = {0, 1, 2}, refon = 0 1 40 80 s t buf_settle settling time of adc reference voltage buffer (6) av cc = av cc(min) to av cc(max) , refvsel = {0, 1, 2}, refon = 1 (internal note should be for buf_int refout=0 or buf_ext=1 ) 0.4 2 s 5.12.11 comparator the comp_e module supports precision slope analog-to-digital conversions, supply voltage supervision, and monitoring of external analog signals. table 5-31 lists the comparator characteristics. table 5-31. comparator_e over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit i avcc_comp comparator operating supply current into avcc, excludes reference resistor ladder cepwrmd = 00, ceon = 1, cersx = 00 (fast) 2.2 v, 3.0 v 12 16 a cepwrmd = 01, ceon = 1, cersx = 00 (medium) 10 14 cepwrmd = 10, ceon = 1, cersx = 00 (slow), t a = 30 c 0.1 0.3 cepwrmd = 10, ceon = 1, cersx = 00 (slow), t a = 85 c 0.3 1.3 i avcc_comp_ref quiescent current of comparator and resistor ladder into avcc, including ref module current cepwrmd = 10, cereflx = 01, cersx = 10, ceon = 1, refon = 0 cerefacc = 0 2.2 v, 3.0 v 31 38 a cerefacc = 1 16 19 v ref reference voltage level cersx = 11, cereflx = 01, cerefacc = 0 1.8 v 1.152 1.2 1.248 v cersx = 11, cereflx = 10, cerefacc = 0 2.2 v 1.92 2.0 2.08 cersx = 11, cereflx = 11, cerefacc = 0 2.7 v 2.40 2.5 2.60 cersx = 11, cereflx = 01, cerefacc = 1 1.8 v 1.10 1.2 1.245 cersx = 11, cereflx = 10, cerefacc = 1 2.2 v 1.90 2.0 2.08 cersx = 11, cereflx = 11, cerefacc = 1 2.7 v 2.35 2.5 2.60 v ic common mode input range 0 v cc ? 1 v v offset input offset voltage cepwrmd = 00 ? 16 16 mv cepwrmd = 01 ? 12 12 cepwrmd = 10 ? 37 37 c in input capacitance cepwrmd = 00 or cepwrmd = 01 10 pf cepwrmd = 10 10 r sin series input resistance on (switch closed) 1 3 k ? off (switch open) 50 m ? t pd propagation delay, response time cef = 0, overdrive 20 mv cepwrmd = 00 193 330 ns cepwrmd = 01 230 400 cepwrmd = 10 5 15 s
62 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated table 5-31. comparator_e (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit t pd,filter propagation delay with filter active cepwrmd = 00 or 01, cef = 1, overdrive 20 mv cefdly = 00 700 1000 ns cefdly = 01 1.0 1.9 s cefdly = 10 2.0 3.7 cefdly = 11 4.0 7.7 t en_cmp comparator enable time ceon = 0 1, v in+ and v in ? from pins, overdrive 20 mv cepwrmd = 00 0.9 1.5 s cepwrmd = 01 0.9 1.5 cepwrmd = 10 15 65 t en_cmp_vref comparator and reference ladder and reference voltage enable time ceon = 0 1, cereflx = 10, cersx = 10 or 11, ceref0 = ceref1 = 0x0f, refon = 0 120 220 s t en_cmp_rl comparator and reference ladder enable time ceon = 0 1, cereflx = 10, cersx = 10, refon = 1, ceref0 = ceref1 = 0x0f 10 30 s v ce_ref reference voltage for a given tap vin = reference into resistor ladder (n = 0 to 31) v in (n + 0.5) / 32 v in (n + 1) / 32 v in (n + 1.5) / 32 v 5.12.12 fram fram is a nonvolatile memory that reads and writes like standard sram. the fram can be read in a similar fashion to sram and needs no special requirements. similarly, any writes to unprotected segments can be written in the same fashion as sram. table 5-32 lists the operating characteristics of the fram. (1) writing to fram does not require a setup sequence or additional power when compared to reading from fram. the fram read current (i read ) is included in the active mode current consumption, i am,fram . (2) fram does not require a special erase sequence. (3) writing into fram is as fast as reading. (4) the maximum read (and write) speed is specified by f system using the appropriate wait state settings (nwaitsx). table 5-32. fram over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit read and write endurance 10 15 cycles t retention data retention duration t j = 25 c 100 years t j = 70 c 40 t j = 85 c 10 i write current to write into fram i read (1) na i erase erase current n/a (2) na t write write time t read (3) ns t read read time nwaitsx = 0 1 / f system (4) ns nwaitsx = 1 2 / f system (4)
63 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 specifications copyright ? 2016 ? 2017, texas instruments incorporated 5.12.13 emulation and debug the msp family supports the standard jtag interface, which requires four signals for sending and receiving data. the jtag signals are shared with general-purpose i/os. the test/sbwtck pin is used to enable the connection of external development tools with the device through spy-bi-wire or jtag debug protocols. the connection is usually enabled when the test/sbwtck is high. when the connection is enabled, the device enters a debug mode. in the debug mode, the times for entry to and wake up from low-power modes may be different compared to normal operation. pay careful attention to the real-time behavior when using low-power modes with the device connected to a development tool. table 5-33 lists the jtag and spy-bi-wire interface characteristics. (1) tools that access the spy-bi-wire and the bsl interfaces must wait for the t sbw,en time after the first transition of the test/sbwtck pin (low to high), before the second transition of the pin (high to low) during the entry sequence. (2) f tck may be restricted to meet the timing requirements of the module selected. table 5-33. jtag and spy-bi-wire interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter v cc min typ max unit i jtag supply current adder when jtag active (but not clocked) 2.2 v, 3.0 v 40 100 a f sbw spy-bi-wire input frequency 2.2 v, 3.0 v 0 10 mhz t sbw,low spy-bi-wire low clock pulse duration 2.2 v, 3.0 v 0.04 15 s t sbw, en spy-bi-wire enable time (test high to acceptance of first clock edge) (1) 2.2 v, 3.0 v 110 s t sbw,rst spy-bi-wire return to normal operation time 15 100 s f tck tck input frequency, 4-wire jtag (2) 2.2 v 0 16 mhz 3.0 v 0 16 r internal internal pulldown resistance on test 2.2 v, 3.0 v 20 35 50 k ? f tclk tclk and mclk frequency during jtag access, no fram access (limited by f system ) 16 mhz t tclk,low/high tclk low or high clock pulse duration, no fram access 25 ns f tclk,fram tclk and mclk frequency during jtag access, including fram access (limited by f system with no fram wait states) 4 mhz t tclk,fram,low/high tclk low or high clock pulse duration, including fram accesses 100 ns
64 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6 detailed description 6.1 overview the ti msp430fr59xx family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals. the architecture, combined with seven low-power modes, is optimized to achieve extended battery life for example in portable measurement applications. the devices features a powerful 16-bit risc cpu, 16-bit registers, and constant generators that contribute to maximum code efficiency. the device is an msp430fr59xx family device with low-energy accelerator (lea) (available only on the msp430fr599x mcus), up to six 16-bit timers, up to eight euscis that support uart, spi, and i 2 c, a comparator, a hardware multiplier, an aes accelerator, a 6-channel dma, an rtc module with alarm capabilities, up to 67 i/o pins, and a high-performance 12-bit adc. 6.2 cpu the msp430 cpu has a 16-bit risc architecture that is highly transparent to the application. all operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. the cpu is integrated with 16 registers that provide reduced instruction execution time. the register-to- register operation execution time is one cycle of the cpu clock. four of the registers, r0 to r3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. the remaining registers are general-purpose registers. peripherals are connected to the cpu using data, address, and control buses. the peripherals can be managed with all instructions. the instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. each instruction can operate on word and byte data. 6.3 low-energy accelerator (lea) for signal processing (msp430fr599x only) the lea module is a hardware engine designed for operations that involve vector-based signal processing, such as fir, iir, and fft. the subsystem offers fast performance and low energy consumption when performing vector-based digital signal processing computations; for performance benchmarks comparing the lea module to using the cpu or other processors, see benchmarking the signal processing capabilities of the low-energy accelerator on msp mcus . the lea module requires mclk to be operational; therefore, the subsystem can run only in active mode or lpm0 (see table 6-1 ). while the lea module is running, the lea data operations are performed on a shared 4kb of ram out of the 8kb of total ram (see table 6-41 ). this shared ram can also be used by the regular application. the msp cpu and the lea module can run simultaneously and independently unless they access the same system ram. direct access to lea registers is not supported, and ti recommends using the optimized digital signal processing (dsp) library for msp microcontrollers for the operations that the lea module supports.
copyright ? 2016 ? 2017, texas instruments incorporated detailed description submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 65 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 6.4 operating modes the mcu has one active mode and seven software selectable low-power modes of operation. an interrupt event can wake up the device from low- power modes lpm0 through lpm4, service the request, and restore back to the low-power mode on return from the interrupt program. low-power modes lpm3.5 and lpm4.5 disable the core supply to minimize power consumption. (1) fram disabled in fram controller a (2) disabling the fram through the fram controller a allows the application to lower the lpm current consumption but the wake-up time increases when fram is accessed (for example, to fetch an interrupt vector). for a wake up that does not access fram (for example, a dma transfer to ram) the wake-up time is not increased. (3) all clocks disabled (4) only while the lea module is performing the task enabled by cpu during am. the lea module cannot be enabled in lpm0. (5) see section 6.4.1 for a detailed description of high-frequency, low-frequency, and unclocked peripherals. (6) see section 6.4.2 , which describes the use of peripherals in lpm3 and lpm4. (7) controlled by smclkoff (8) activate svs (svshe = 1) results in higher current consumption. svs is not included in typical current consumption. (9) svshe = 1 (10) svshe = 0 table 6-1. operating modes mode am lpm0 lpm1 lpm2 lpm3 lpm4 lpm3.5 lpm4.5 active active, fram off (1) cpu off (2) cpu off standby standby off rtc only shutdown with svs shutdown without svs maximum system clock 16 mhz 16 mhz 16 mhz 50 khz 50 khz 0 (3) 50 khz 0 (3) typical current consumption, t a = 25 c 120 a/mhz 65 a/mhz 92 a at 1 mhz 40 a at 1 mhz 1.0 a 0.7 a 0.5 a 0.45 a 0.3 a 0.07 a typical wake-up time n/a instant 6 s 6 s 7 s 7 s 250 s 250 s 400 s wake-up events n/a all all lf rtc i/o comp lf rtc i/o comp i/o comp rtc i/o i/o cpu on off off off off off reset reset lea (msp430fr599x only) on on (4) off off off off off reset reset fram on off (1) standby (or off (1) ) off off off off off off high-frequency peripherals (5) available available available off off off reset reset low-frequency peripherals (5) available available available available available (6) off rtc reset unclocked peripherals (5) available available available available available (6) available (6) reset reset mclk on on (4) off off off off off off off smclk optional (7) optional (7) optional (7) off off off off off aclk on on on on on off off off full retention yes yes yes yes yes yes no no svs always always always optional (8) optional (8) optional (8) optional (8) on (9) off (10) brownout always always always always always always always always
66 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.4.1 peripherals in low-power modes peripherals can be in different states that impact the achievable power modes of the device. the states depend on the operational modes of the peripherals (see table 6-2 ). the states are: ? a peripheral is in a high-frequency state if it requires or uses a clock with a "high" frequency of more than 50 khz. ? a peripheral is in a low-frequency state if it requires or uses a clock with a "low" frequency of 50 khz or less. ? a peripheral is in an unclocked state if it does not require or use an internal clock. if the cpu requests a power mode that does not support the current state of all active peripherals, the device does not enter the requested power mode, but it does enter a power mode that still supports the current state of the peripherals, except if an external clock is used. if an external clock is used, the application must use the correct frequency range for the requested power mode. (1) peripherals are in a state that requires or uses a clock with a " high " frequency of more than 50 khz (2) peripherals are in a state that requires or uses a clock with a " low " frequency of 50 khz or less. (3) peripherals are in a state that does not require or does not use an internal clock. (4) the dma always transfers data in active mode but can wait for a trigger in any low-power mode. a dma trigger during a low-power mode causes a temporary transition into active mode for the time of the transfer. (5) this peripheral operates during active mode only and will delay the transition into a low-power mode until its operation is completed. table 6-2. peripheral states peripheral in high-frequency state (1) in low-frequency state (2) in unclocked state (3) wdt clocked by smclk clocked by aclk not applicable dma (4) not applicable not applicable waiting for a trigger rtc_c not applicable clocked by lfxt not applicable timer_a tax clocked by smclk or clocked by external clock > 50 khz clocked by aclk or clocked by external clock 50 khz clocked by external clock 50 khz timer_b tbx clocked by smclk or clocked by external clock > 50 khz clocked by aclk or clocked by external clock 50 khz clocked by external clock 50 khz eusci_ax in uart mode clocked by smclk clocked by aclk waiting for first edge of start bit. eusci_ax in spi master mode clocked by smclk clocked by aclk not applicable eusci_ax in spi slave mode clocked by external clock > 50 khz clocked by external clock 50 khz clocked by external clock 50 khz eusci_bx in i 2 c master mode clocked by smclk or clocked by external clock > 50 khz clocked by aclk or clocked by external clock 50 khz not applicable eusci_bx in i 2 c slave mode clocked by external clock > 50 khz clocked by external clock 50 khz waiting for start condition or clocked by external clock 50 khz eusci_bx in spi master mode clocked by smclk clocked by aclk not applicable eusci_bx in spi slave mode clocked by external clock > 50 khz clocked by external clock 50 khz clocked by external clock 50 khz adc12_b clocked by smclk or by modosc clocked by aclk waiting for a trigger ref_a not applicable not applicable always comp_e not applicable not applicable always crc (5) not applicable not applicable not applicable mpy (5) not applicable not applicable not applicable aes (5) not applicable not applicable not applicable
67 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.4.2 idle currents of peripherals in lpm3 and lpm4 most peripherals can be operational in lpm3 if clocked by aclk. some modules are operational in lpm4, because they do not require a clock to operate (for example, the comparator). activating a peripheral in lpm3 or lpm4 increases the current consumption due to its active supply current contribution but also due to an additional idle current. to reduce the idle current adder, certain peripherals are grouped together (see table 6-3 ). to achieve optimal current consumption, use modules within one group and limit the number of groups with active modules. modules not listed in table 6-3 are either already included in the standard lpm3 current consumption or cannot be used in lpm3 or lpm4. the idle current adder is very small at room temperature (25 c) but increases at high temperatures (85 c). see the i idle current parameters in section 5 for details. table 6-3. peripheral groups group a group b group c timer ta1 timer ta0 timer ta4 timer ta2 timer ta3 eusci_a2 timer tb0 comparator eusci_a3 eusci_a0 adc12_b eusci_b1 eusci_a1 ref_a eusci_b2 eusci_b0 eusci_b3 6.5 interrupt vector table and signatures the interrupt vectors, the power-up start address and signatures are in the address range 0ffffh to 0ff80h. figure 6-1 summarizes the content of this address range. figure 6-1. interrupt vectors, signatures and passwords the power-up start address or reset vector is at 0ffffh to 0fffeh. this location contains a 16-bit address pointing to the start address of the application program. the interrupt vectors start at 0fffdh and extend to lower addresses. each vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. table 6-4 shows the device specific interrupt vector locations. the vectors programmed into the address range from 0ffffh to 0ffe0h are used as bsl password (if enabled by the corresponding signature). 0ffffh jtag password bsl password reset vector interrupt vectors signatures reserved 0ff88h0ff80h 0ffe0h
68 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated (1) multiple source flags (2) a reset is generated if the cpu tries to fetch instructions from peripheral space. (3) (non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot disable it. (4) only on devices with adc, otherwise reserved. the signatures are at 0ff80h and extend to higher addresses. signatures are evaluated during device start-up. table 6-5 lists the device-specific signature locations. a jtag password can be programmed starting at address 0ff88h and extending to higher addresses. the password can extend into the interrupt vector locations using the interrupt vector addresses as additional bits for the password. the length of the jtag password depends on the jtag signature. see the system resets, interrupts, and operating modes, system control module (sys) chapter in the msp430fr58xx, msp430fr59xx, msp430fr68xx, msp430fr69xx family user ' s guide for details. table 6-4. interrupt sources, flags, and vectors interrupt source interrupt flag system interrupt word address priority system reset power up, brownout, supply supervisor external reset rst watchdog time-out (watchdog mode) wdt, frctl mpu, cs, pmm password violation fram uncorrectable bit error detection mpu segment violation software por, bor svshifg pmmrstifg wdtifg wdtpw, frctlpw, mpupw, cspw, pmmpw ubdifg mpusegiifg, mpuseg1ifg, mpuseg2ifg, mpuseg3ifg pmmporifg, pmmborifg (sysrstiv) (1) (2) reset 0fffeh highest system nmi vacant memory access jtag mailbox fram access time error fram write protection error fram bit error detection mpu segment violation vmaifg jmbinifg, jmboutifg accteifg, wpifg cbdifg, ubdifg mpusegiifg, mpuseg1ifg, mpuseg2ifg, mpuseg3ifg (syssniv) (1) (3) (non)maskable 0fffch user nmi external nmi oscillator fault nmiifg, ofifg (sysuniv) (1) (3) (non)maskable 0fffah comparator_e ceifg, ceiifg (ceiv) (1) maskable 0fff8h tb0 tb0ccr0.ccifg maskable 0fff6h tb0 tb0ccr1.ccifg ... tb0ccr6.ccifg, tb0ctl.tbifg (tb0iv) (1) maskable 0fff4h watchdog timer (interval timer mode) wdtifg maskable 0fff2h eusci_a0 receive or transmit uca0ifg: ucrxifg, uctxifg (spi mode) uca0ifg: ucsttifg, uctxcptifg, ucrxifg, uctxifg (uart mode) (uca0iv) (1) maskable 0fff0h eusci_b0 receive or transmit ucb0ifg: ucrxifg, uctxifg (spi mode) ucb0ifg: ucalifg, ucnackifg, ucsttifg, ucstpifg, ucrxifg0, uctxifg0, ucrxifg1, uctxifg1, ucrxifg2, uctxifg2, ucrxifg3, uctxifg3, uccntifg, ucbit9ifg (i 2 c mode) (ucb0iv) (1) maskable 0ffeeh adc12_b adc12ifg0 to adc12ifg31 adc12loifg, adc12inifg, adc12hiifg, adc12rdyifg, adc21ovifg, adc12tovifg (adc12iv) (1) (4) maskable 0ffech ta0 ta0ccr0.ccifg maskable 0ffeah
69 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated table 6-4. interrupt sources, flags, and vectors (continued) interrupt source interrupt flag system interrupt word address priority ta0 ta0ccr1.ccifg, ta0ccr2.ccifg, ta0ctl.taifg (ta0iv) (1) maskable 0ffe8h eusci_a1 receive or transmit uca1ifg: ucrxifg, uctxifg (spi mode) uca1ifg: ucsttifg, uctxcptifg, ucrxifg, uctxifg (uart mode) (uca1iv) (1) maskable 0ffe6h dma dma0ctl.dmaifg, dma1ctl.dmaifg, dma2ctl.dmaifg (dmaiv) (1) maskable 0ffe4h ta1 ta1ccr0.ccifg maskable 0ffe2h ta1 ta1ccr1.ccifg, ta1ccr2.ccifg, ta1ctl.taifg (ta1iv) (1) maskable 0ffe0h i/o port p1 p1ifg.0 to p1ifg.7 (p1iv) (1) maskable 0ffdeh ta2 ta2ccr0.ccifg maskable 0ffdch ta2 ta2ccr1.ccifg ta2ctl.taifg (ta2iv) (1) maskable 0ffdah i/o port p2 p2ifg.0 to p2ifg.7 (p2iv) (1) maskable 0ffd8h ta3 ta3ccr0.ccifg maskable 0ffd6h ta3 ta3ccr1.ccifg ta3ctl.taifg (ta3iv) (1) maskable 0ffd4h i/o port p3 p3ifg.0 to p3ifg.7 (p3iv) (1) maskable 0ffd2h i/o port p4 p4ifg.0 to p4ifg.2 (p4iv) (1) maskable 0ffd0h rtc_c rtcrdyifg, rtctevifg, rtcaifg, rt0psifg, rt1psifg, rtcofifg (rtciv) (1) maskable 0ffceh aes aesrdyifg maskable 0ffcch ta4 ta4ccr0.ccifg maskable 0ffcah ta4 ta4ccr1.ccifg ta4ctl.taifg (ta4iv) (1) maskable 0ffc8h i/o port p5 p5ifg.0 to p5ifg.2 (p5iv) (1) maskable 0ffc6h i/o port p6 p6ifg.0 to p6ifg.2 (p6iv) (1) maskable 0ffc4h eusci_a2 receive or transmit uca2ifg: ucrxifg, uctxifg (spi mode) uca2ifg: ucsttifg, uctxcptifg, ucrxifg, uctxifg (uart mode) (uca2iv) (1) maskable 0ffc2h eusci_a3 receive or transmit uca3ifg: ucrxifg, uctxifg (spi mode) uca3ifg: ucsttifg, uctxcptifg, ucrxifg, uctxifg (uart mode) (uca3iv) (1) maskable 0ffc0h eusci_b1 receive or transmit ucb1ifg: ucrxifg, uctxifg (spi mode) ucb1ifg: ucalifg, ucnackifg, ucsttifg, ucstpifg, ucrxifg0, uctxifg0, ucrxifg1, uctxifg1, ucrxifg2, uctxifg2, ucrxifg3, uctxifg3, uccntifg, ucbit9ifg (i 2 c mode) (ucb1iv) (1) maskable 0ffbeh
70 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated table 6-4. interrupt sources, flags, and vectors (continued) interrupt source interrupt flag system interrupt word address priority eusci_b2 receive or transmit ucb2ifg: ucrxifg, uctxifg (spi mode) ucb2ifg: ucalifg, ucnackifg, ucsttifg, ucstpifg, ucrxifg0, uctxifg0, ucrxifg1, uctxifg1, ucrxifg2, uctxifg2, ucrxifg3, uctxifg3, uccntifg, ucbit9ifg (i 2 c mode) (ucb2iv) (1) maskable 0ffbch eusci_b3 receive or transmit ucb3ifg: ucrxifg, uctxifg (spi mode) ucb3ifg: ucalifg, ucnackifg, ucsttifg, ucstpifg, ucrxifg0, uctxifg0, ucrxifg1, uctxifg1, ucrxifg2, uctxifg2, ucrxifg3, uctxifg3, uccntifg, ucbit9ifg (i 2 c mode) (ucb3iv) (1) maskable 0ffbah i/o port p7 p7ifg.0 to p7ifg.2 (p7iv) (1) maskable 0ffb8h i/o port p8 p6ifg.0 to p6ifg.2 (p8iv) (1) maskable 0ffb6h lea (msp430fr599x only) cmdifg, sdiifg, oorifg,tifg, covlifg leaiv (1) maskable 0ffb4h lowest (1) must not contain 0aaaah if used as the jtag password. table 6-5. signatures signature word address ip encapsulation signature 2 0ff8ah ip encapsulation signature 1 (1) 0ff88h bsl signature 2 0ff86h bsl signature 1 0ff84h jtag signature 2 0ff82h jtag signature 1 0ff80h 6.6 bootloader (bsl) the bsl can program the fram or ram using a uart serial interface (frxxxx devices) or an i 2 c interface (frxxxx1 devices). access to the device memory through the bsl is protected by an user- defined password. table 6-6 lists the pins that are required to use the bsl. bsl entry requires a specific entry sequence on the rst/nmi/sbwtdio and test/sbwtck pins. for a complete description of the features of the bsl and its implementation, see the msp430fr57xx, fr58xx, fr59xx, fr68xx, and fr69xx bootloader (bsl) user ' s guide . visit bootloader (bsl) for msp low-power microcontrollers for more information.
71 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated table 6-6. bsl pin requirements and functions device signal bsl function rst/nmi/sbwtdio entry sequence signal test/sbwtck entry sequence signal p2.0 devices with uart bsl (frxxxx): data transmit p2.1 devices with uart bsl (frxxxx): data receive p1.6 devices with i 2 c bsl (frxxxx1): data p1.7 devices with i 2 c bsl (frxxxx1): clock vcc power supply vss ground supply 6.7 jtag operation 6.7.1 jtag standard interface the msp family supports the standard jtag interface, which requires four signals for sending and receiving data. the jtag signals are shared with general-purpose i/o. the test/sbwtck pin is used to enable the jtag signals. in addition to these signals, the rst/nmi/sbwtdio is required to interface with msp development tools and device programmers. table 6-7 lists the jtag pin requirements. for further details on interfacing to development tools and device programmers, see the msp430 hardware tools user ' s guide . for a complete description of the features of the jtag interface and its implementation, see msp430 programming with the jtag interface . table 6-7. jtag pin requirements and functions device signal direction function pj.3/tck in jtag clock input pj.2/tms in jtag state control pj.1/tdi/tclk in jtag data input, tclk input pj.0/tdo out jtag data output test/sbwtck in enable jtag pins rst/nmi/sbwtdio in external reset vcc power supply vss ground supply 6.7.2 spy-bi-wire interface in addition to the standard jtag interface, the msp family supports the two wire spy-bi-wire interface. spy-bi-wire can be used to interface with msp development tools and device programmers. the spy-bi- wire interface pin requirements are shown in table 6-8 . for further details on interfacing to development tools and device programmers, see the msp430 hardware tools user ' s guide . for a complete description of the features of the jtag interface and its implementation, see msp430 programming with the jtag interface . table 6-8. spy-bi-wire pin requirements and functions device signal direction function test/sbwtck in spy-bi-wire clock input rst/nmi/sbwtdio in, out spy-bi-wire data input and output vcc power supply vss ground supply
72 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.8 fram controller a (frctl_a) the fram can be programmed through the jtag port, spy-bi-wire (sbw), the bsl, or in system by the cpu (also see table 6-45 for control and configuration registers). features of the fram include: ? ultra-low-power ultra-fast-write nonvolatile memory ? byte and word access capability ? programmable wait state generation ? error correction coding (ecc) note wait states for mclk frequencies > 8 mhz, wait states must be configured following the flow described in the "wait state control" section of the fram controller a (frctrl_a) chapter in the msp430fr58xx, msp430fr59xx, msp430fr68xx, msp430fr69xx family user ' s guide . for important software design information regarding fram including but not limited to partitioning the memory layout according to application-specific code, constant, and data space requirements, the use of fram to optimize application energy consumption, and the use of the memory protection unit (mpu) to maximize application robustness by protecting the program code against unintended write accesses, see msp430 ? fram technology ? how to and best practices . 6.9 ram the ram is made up of three sectors: sector 0 = 2kb, sector 1 = 2kb, sector 2 = 4kb (shared with the lea module). each sector can be individually powered down in lpm3 and lpm4 to save leakage. data is lost when sectors are powered down in lpm3 and lpm4. see table 6-47 for control and configuration registers. 6.10 tiny ram tiny ram provides 22 bytes of ram in addition to the complete ram (see table 6-41 ). this memory is always available, even in lpm3 and lpm4, while the complete ram can be powered down in lpm3 and lpm4. tiny ram can be used to hold data or a very small stack when the complete ram is powered down in lpm3 and lpm4. no memory is available in lpmx.5. 6.11 memory protection unit (mpu) including ip encapsulation the fram can be protected by the mpu from inadvertent cpu execution, read access, or write access. see table 6-67 for control and configuration registers. features of the mpu include: ? ip encapsulation with programmable boundaries in steps of 1kb (prevents reads from "outside"; for example, through jtag or by non-ip software). ? main memory partitioning is programmable up to three segments in steps of 1kb. ? access rights of each segment can be individually selected (main and information memory). ? access violation flags with interrupt capability for easy servicing of access violations.
73 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.12 peripherals peripherals are connected to the cpu through data, address, and control buses. the peripherals can be managed using all instructions. for complete module descriptions, see the msp430fr58xx, msp430fr59xx, msp430fr68xx, msp430fr69xx family user ' s guide . 6.12.1 digital i/o up to nine 8-bit i/o ports are implemented (see table 6-52 through table 6-56 for control and configuration registers): ? all individual i/o bits are independently programmable. ? any combination of input, output, and interrupt conditions is possible. ? programmable pullup or pulldown on all ports. ? edge-selectable interrupt and lpm3.5 and lpm4.5 wake-up input capability is available for all pins of ports p1 to p8. ? read and write access to port control registers is supported by all instructions. ? ports can be accessed byte-wise or word-wise in pairs. ? all pins of ports p1 to p8, and pj support capacitive touch functionality. ? no cross-currents during start-up. note configuration of digital i/os after bor reset to prevent any cross currents during start-up of the device, all port pins are high-impedance with schmitt triggers and their module functions disabled. to enable the i/o functionality after a bor reset, first configure the ports and then clear the locklpm5 bit. for details, see the configuration after reset section of the digital i/o chapter in the msp430fr58xx, msp430fr59xx, msp430fr68xx, msp430fr69xx family user ' s guide . 6.12.2 oscillator and clock system (cs) the clock system includes support for a 32-khz watch-crystal oscillator xt1 (lf), an internal very-low- power low-frequency oscillator (vlo), an integrated internal digitally controlled oscillator (dco), and a high-frequency crystal oscillator xt2 (hf). the clock system module is designed to meet the requirements of both low system cost and low power consumption. a fail-safe mechanism exists for all crystal sources. see table 6-49 for control and configuration registers. the clock system module provides the following clock signals: ? auxiliary clock (aclk). aclk can be sourced from a 32-khz watch crystal (lfxt1), the internal vlo, or a digital external low-frequency ( < 50 khz) clock source. ? main clock (mclk), the system clock used by the cpu. mclk can be sourced from a high-frequency crystal (hfxt2), the internal dco, a 32-khz watch crystal (lfxt1), the internal vlo, or a digital external clock source. ? sub-main clock (smclk), the subsystem clock used by the peripheral modules. smclk can be sourced by same sources made available to mclk. 6.12.3 power-management module (pmm) the pmm includes an integrated voltage regulator that supplies the core voltage to the device. the pmm also includes supply voltage supervisor (svs) and brownout protection. the brownout circuit provides the proper internal reset signal to the device during power on and power off. the svs circuitry detects if the supply voltage drops below a safe level and below a user-selectable level. svs circuitry is available on the primary and core supplies. see table 6-44 for control and configuration registers.
74 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.12.4 hardware multiplier (mpy) the multiplication operation is supported by a dedicated peripheral module. the module performs operations with 32-, 24-, 16-, and 8-bit operands. the module supports signed multiplication, unsigned multiplication, signed multiply-and-accumulate, and unsigned multiply-and-accumulate operations. see table 6-65 for control and configuration registers. 6.12.5 real-time clock (rtc_c) the rtc_c module contains an integrated real-time clock (rtc) with the following features: ? calendar mode with leap year correction ? general-purpose counter mode the internal calendar compensates for months with fewer than 31 days and includes leap year correction. the rtc_c also supports flexible alarm functions and offset-calibration hardware. rtc operation is available in lpm3.5 modes to minimize power consumption. see table 6-64 for control and configuration registers. 6.12.6 watchdog timer (wdt_a) the primary function of the wdt_a module is to perform a controlled system restart if a software problem occurs. if the selected time interval expires, a system reset is generated. if the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. table 6-9 lists the clocks that can source wdt_a. see table 6-48 for control and configuration registers. table 6-9. wdt_a clocks wdtssel normal operation (watchdog and interval timer mode) 00 smclk 01 aclk 10 vloclk 11 lfmodclk 6.12.7 system module (sys) the sys module manages many of the system functions within the device. these include power-on reset (por) and power-up clear (puc) handling, nmi source selection and management, reset interrupt vector generators (see table 6-10 ), bootloader (bsl) entry mechanisms, and configuration management (device descriptors). the sys module also includes a data exchange mechanism through jtag called a jtag mailbox that can be used in the application. see table 6-50 for control and configuration registers.
75 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated (1) reserved on msp430fr596x. table 6-10. system module interrupt vector registers interrupt vector register address interrupt event value priority sysrstiv, system reset 019eh no interrupt pending 00h brownout (bor) 02h highest rstifg rst/nmi (bor) 04h pmmswbor software bor (bor) 06h lpmx.5 wake up (bor) 08h security violation (bor) 0ah reserved 0ch svshifg svsh event (bor) 0eh reserved 10h reserved 12h pmmswpor software por (por) 14h wdtifg watchdog timeout (puc) 16h wdtpw password violation (puc) 18h frctlpw password violation (puc) 1ah uncorrectable fram bit error detection (puc) 1ch peripheral area fetch (puc) 1eh pmmpw pmm password violation (puc) 20h mpupw mpu password violation (puc) 22h cspw cs password violation (puc) 24h mpusegipifg encapsulated ip memory segment violation (puc) 26h mpusegiifg information memory segment violation (puc) 28h mpuseg1ifg segment 1 memory violation (puc) 2ah mpuseg2ifg segment 2 memory violation (puc) 2ch mpuseg3ifg segment 3 memory violation (puc) 2eh reserved 30h to 3eh lowest syssniv, system nmi 019ch no interrupt pending 00h reserved 02h highest uncorrectable fram bit error detection 04h fram access time error 06h mpusegipifg encapsulated ip memory segment violation 08h mpusegiifg information memory segment violation 0ah mpuseg1ifg segment 1 memory violation 0ch mpuseg2ifg segment 2 memory violation 0eh mpuseg3ifg segment 3 memory violation 10h vmaifg vacant memory access 12h jmbinifg jtag mailbox input 14h jmboutifg jtag mailbox output 16h correctable fram bit error detection 18h fram write protection detection 1ah lea time-out fault (1) 1ch lea command fault (1) 1eh lowest
76 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated table 6-10. system module interrupt vector registers (continued) interrupt vector register address interrupt event value priority sysuniv, user nmi 019ah no interrupt pending 00h nmiifg nmi pin 02h highest ofifg oscillator fault 04h reserved 06h reserved 08h reserved 0ah to 1eh lowest (1) if a reserved trigger source is selected, no trigger is generated. (2) reserved on msp430fr596x. 6.12.8 dma controller the dma controller allows movement of data from one memory address to another without cpu intervention. for example, the dma controller can be used to move data from the adc12_b conversion memory to ram. using the dma controller can increase the throughput of peripheral modules. the dma controller reduces system power consumption by allowing the cpu to remain in sleep mode, without having to awaken to move data to or from a peripheral. see table 6-66 for control and configuration registers. table 6-11 lists the available dma triggers. table 6-11. dma trigger assignments (1) trigger channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 0 dmareq dmareq dmareq dmareq dmareq dmareq 1 ta0ccr0 ccifg ta0ccr0 ccifg ta0ccr0 ccifg ta0ccr0 ccifg ta0ccr0 ccifg ta0ccr0 ccifg 2 ta0ccr2 ccifg ta0ccr2 ccifg ta0ccr2 ccifg ta0ccr2 ccifg ta0ccr2 ccifg ta0ccr2 ccifg 3 ta1ccr0 ccifg ta1ccr0 ccifg ta1ccr0 ccifg ta1ccr0 ccifg ta1ccr0 ccifg ta1ccr0 ccifg 4 ta1ccr2 ccifg ta1ccr2 ccifg ta1ccr2 ccifg ta1ccr2 ccifg ta1ccr2 ccifg ta1ccr2 ccifg 5 ta2ccr0 ccifg ta2ccr0 ccifg ta2ccr0 ccifg ta2ccr0 ccifg ta2ccr0 ccifg ta2ccr0 ccifg 6 ta3ccr0 ccifg ta3ccr0 ccifg ta3ccr0 ccifg ta3ccr0 ccifg ta3ccr0 ccifg ta3ccr0 ccifg 7 tb0ccr0 ccifg tb0ccr0 ccifg tb0ccr0 ccifg tb0ccr0 ccifg tb0ccr0 ccifg tb0ccr0 ccifg 8 tb0ccr2 ccifg tb0ccr2 ccifg tb0ccr2 ccifg tb0ccr2 ccifg tb0ccr2 ccifg tb0ccr2 ccifg 9 ta4ccr0 ccifg ta4ccr0 ccifg ta4ccr0 ccifg ta4ccr0 ccifg ta4ccr0 ccifg ta4ccr0 ccifg 10 reserved reserved reserved reserved reserved reserved 11 aes trigger 0 aes trigger 0 aes trigger 0 aes trigger 0 aes trigger 0 aes trigger 0 12 aes trigger 1 aes trigger 1 aes trigger 1 aes trigger 1 aes trigger 1 aes trigger 1 13 aes trigger 2 aes trigger 2 aes trigger 2 aes trigger 2 aes trigger 2 aes trigger 2 14 uca0rxifg uca0rxifg uca0rxifg uca2rxifg uca2rxifg uca2rxifg 15 uca0txifg uca0txifg uca0txifg uca2txifg uca2txifg uca2txifg 16 uca1rxifg uca1rxifg uca1rxifg uca3rxifg uca3rxifg uca3rxifg 17 uca1txifg uca1txifg uca1txifg uca3txifg uca3txifg uca3txifg 18 ucb0rxifg (spi) ucb0rxifg0 (i 2 c) ucb0rxifg (spi) ucb0rxifg0 (i 2 c) ucb0rxifg (spi) ucb0rxifg0 (i 2 c) ucb1rxifg (spi) ucb1rxifg0 (i 2 c) ucb2rxifg (spi) ucb2rxifg0 (i 2 c) ucb3rxifg (spi) ucb3rxifg0 (i 2 c) 19 ucb0txifg (spi) ucb0txifg0 (i 2 c) ucb0txifg (spi) ucb0txifg0 (i 2 c) ucb0txifg (spi) ucb0txifg0 (i 2 c) ucb1txifg (spi) ucb1txifg0 (i 2 c) ucb2txifg (spi) ucb2txifg0 (i 2 c) ucb3txifg (spi) ucb3txifg0 (i 2 c) 20 ucb0rxifg1 (i 2 c) ucb0rxifg1 (i 2 c) ucb0rxifg1 (i 2 c) ucb1rxifg1 (i 2 c) ucb2rxifg1 (i 2 c) ucb3rxifg1 (i 2 c) 21 ucb0txifg1 (i 2 c) ucb0txifg1 (i 2 c) ucb0txifg1 (i 2 c) ucb1txifg1 (i 2 c) ucb2txifg1 (i 2 c) ucb3txifg1 (i 2 c) 22 ucb0rxifg2 (i 2 c) ucb0rxifg2 (i 2 c) ucb0rxifg2 (i 2 c) ucb1rxifg2 (i 2 c) ucb2rxifg2 (i 2 c) ucb3rxifg2 (i 2 c) 23 ucb0txifg2 (i 2 c) ucb0txifg2 (i 2 c) ucb0txifg2 (i 2 c) ucb1txifg2 (i 2 c) ucb2txifg2 (i 2 c) ucb3txifg2 (i 2 c) 24 ucb0rxifg3 (i 2 c) ucb0rxifg3 (i 2 c) ucb0rxifg3 (i 2 c) ucb1rxifg3 (i 2 c) ucb2rxifg3 (i 2 c) ucb3rxifg3 (i 2 c) 25 ucb0txifg3 (i 2 c) ucb0txifg3 (i 2 c) ucb0txifg3 (i 2 c) ucb1txifg3 (i 2 c) ucb2txifg3 (i 2 c) ucb3txifg3 (i 2 c) 26 adc12 end of conversion adc12 end of conversion adc12 end of conversion adc12 end of conversion adc12 end of conversion adc12 end of conversion 27 lea ready (2) lea ready (2) lea ready (2) lea ready (2) lea ready (2) lea ready (2)
77 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated table 6-11. dma trigger assignments (1) (continued) trigger channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 28 reserved reserved reserved reserved reserved reserved 29 mpy ready mpy ready mpy ready mpy ready mpy ready mpy ready 30 dma2ifg dma0ifg dma1ifg dma5ifg dma3ifg dma4ifg 31 dmae0 dmae0 dmae0 dmae0 dmae0 dmae0 (1) only on devices with adc. 6.12.9 enhanced universal serial communication interface (eusci) the eusci modules are used for serial data communication. the eusci module supports synchronous communication protocols such as spi (3 pin or 4 pin) and i 2 c, and asynchronous communication protocols such as uart, enhanced uart with automatic baud-rate detection, and irda. the eusci_an module provides support for spi (3 pin or 4 pin), uart, enhanced uart, and irda. the eusci_bn module provides support for spi (3 pin or 4 pin) and i 2 c. up to four eusci_a modules and up to four eusci_b modules are implemented. see table 6-68 through table 6-75 for control and configuration registers. 6.12.10 ta0, ta1, and ta4 ta0, ta1, and ta4 are 16-bit timers and counters (timer_a type) with three (ta0 and ta1) or two (ta4) capture/compare registers each. each timer can support multiple captures or compares, pwm outputs, and interval timing (see table 6-12 , table 6-13 , and table 6-14 ). each timer has extensive interrupt capabilities. interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. see table 6-57 , table 6-58 , and table 6-76 for control and configuration registers. table 6-12. ta0 signal connections input port pin device input signal module input signal module block module output signal device output signal output port pin p1.2 ta0clk taclk timer n/a n/a aclk (internal) aclk smclk (internal) smclk p1.2 ta0clk inclk p1.6 ta0.0 cci0a ccr0 ta0 ta0.0 p1.6 p2.3 ta0.0 cci0b p2.3 dvss gnd dvcc v cc p1.0 ta0.1 cci1a ccr1 ta1 ta0.1 p1.0 cout (internal) cci1b adc12(internal) (1) adc12shsx = {1} dvss gnd dvcc v cc p1.1 ta0.2 cci2a ccr2 ta2 ta0.2 p1.1 aclk (internal) cci2b dvss gnd dvcc v cc
78 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated (1) only on devices with adc. table 6-13. ta1 signal connections input port pin device input signal module input signal module block module output signal device output signal output port pin p1.1 ta1clk taclk timer n/a n/a aclk (internal) aclk smclk (internal) smclk p1.1 ta1clk inclk p1.7 ta1.0 cci0a ccr0 ta0 ta1.0 p1.7 p2.4 ta1.0 cci0b p2.4 dvss gnd dvcc v cc p1.2 ta1.1 cci1a ccr1 ta1 ta1.1 p1.2 cout (internal) cci1b adc12(internal) (1) adc12shsx = {4} dvss gnd dvcc v cc p1.3 ta1.2 cci2a ccr2 ta2 ta1.2 p1.3 aclk (internal) cci2b dvss gnd dvcc v cc (1) only on devices with adc. table 6-14. ta4 signal connections input port pin device input signal module input signal module block module output signal device output signal output port pin p5.2 ta4clk taclk timer n/a n/a aclk (internal) aclk smclk (internal) smclk p5.2 ta4clk inclk p5.6 ta4.0 cci0a ccr0 ta0 ta4.0 p7.4 ta4.0 cci0b dvss gnd dvcc v cc p5.7 ta4.1 cci1a ccr1 ta1 ta4.1 p7.3 ta4.1 cci1b adc12(internal) (1) adc12shsx = {7} dvss gnd dvcc v cc
79 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated (1) only on devices with adc 6.12.11 ta2 and ta3 ta2 and ta3 are 16-bit timers and counters (timer_a type) with two capture/compare registers each and with internal connections only. each timer can support multiple captures or compares, pwm outputs, and interval timing (see table 6-15 and table 6-16 ). each timer has extensive interrupt capabilities. interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. see table 6-60 and table 6-62 for control and configuration registers. table 6-15. ta2 signal connections device input signal module input name module block module output signal device output signal cout (internal) taclk timer n/a aclk (internal) aclk smclk (internal) smclk from capacitive touch i/o 0 (internal) inclk ta3 ccr0 output (internal) cci0a ccr0 ta0 ta3 cci0a input aclk (internal) cci0b dvss gnd dvcc v cc from capacitive touch i/o 0 (internal) cci1a ccr1 ta1 adc12(internal) (1) adc12shsx = {5} cout (internal) cci1b dvss gnd dvcc v cc (1) only on devices with adc table 6-16. ta3 signal connections device input signal module input name module block module output signal device output signal cout (internal) taclk timer n/a aclk (internal) aclk smclk (internal) smclk from capacitive touch i/o 1 (internal) inclk ta2 ccr0 output (internal) cci0a ccr0 ta0 ta2 cci0a input aclk (internal) cci0b dvss gnd dvcc v cc from capacitive touch i/o 1 (internal) cci1a ccr1 ta1 adc12(internal) (1) adc12shsx = {6} cout (internal) cci1b dvss gnd dvcc v cc
80 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated (1) only on devices with adc. 6.12.12 tb0 tb0 is a 16-bit timer and counter (timer_b type) with seven capture/compare registers. tb0 can support multiple captures or compares, pwm outputs, and interval timing (see table 6-17 ). tb0 has extensive interrupt capabilities. interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. see table 6-59 for control and configuration registers. table 6-17. tb0 signal connections input port pin device input signal module input signal module block module output signal device output signal output port pin p2.0 tb0clk tbclk timer n/a n/a aclk (internal) aclk smclk (internal) smclk p2.0 tb0clk inclk p2.1 tb0.0 cci0a ccr0 tb0 tb0.0 p2.1 p2.5 tb0.0 cci0b p2.5 dvss gnd adc12 (internal) (1) adc12shsx = {2} dvcc v cc p1.4 tb0.1 cci1a ccr1 tb1 tb0.1 p1.4 cout (internal) cci1b p2.6 dvss gnd adc12 (internal) (1) adc12shsx = {3} dvcc v cc p1.5 tb0.2 cci2a ccr2 tb2 tb0.2 p1.5 aclk (internal) cci2b p2.2 dvss gnd dvcc v cc p3.4 tb0.3 cci3a ccr3 tb3 tb0.3 p3.4 p1.6 tb0.3 cci3b p1.6 dvss gnd dvcc v cc p3.5 tb0.4 cci4a ccr4 tb4 tb0.4 p3.5 p1.7 tb0.4 cci4b p1.7 dvss gnd dvcc v cc p3.6 tb0.5 cci5a ccr5 tb5 tb0.5 p3.6 p4.4 tb0.5 cci5b p4.4 dvss gnd dvcc v cc p3.7 tb0.6 cci6a ccr6 tb6 tb0.6 p3.7 p2.0 tb0.6 cci6b p2.0 dvss gnd dvcc v cc
81 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.12.13 adc12_b the adc12_b module supports fast 12-bit analog-to-digital conversions with differential and single-ended inputs. the module implements a 12-bit sar core, sample select control, a reference generator, and a conversion result buffer. a window comparator with lower and upper limits allows cpu-independent result monitoring with three window comparator interrupt flags. see table 6-77 for control and configuration registers. table 6-18 summarizes the available external trigger sources. table 6-19 lists the available multiplexing between internal and external analog inputs. table 6-18. adc12_b trigger signal connections adc12shsx connected trigger source binary decimal 000 0 software (adc12sc) 001 1 ta0 ccr1 output 010 2 tb0 ccr0 output 011 3 tb0 ccr1 output 100 4 ta1 ccr1 output 101 5 ta2 ccr1 output 110 6 ta3 ccr1 output 111 7 ta4 ccr1 output (1) n/a = no internal signal is available on this device. table 6-19. adc12_b external and internal signal mapping control bit in adc12ctl3 register external adc input (control bit = 0) internal adc input (control bit = 1) adc12batmap a31 battery monitor adc12tcmap a30 temperature sensor adc12ch0map a29 n/a (1) adc12ch1map a28 n/a (1) adc12ch2map a27 n/a (1) adc12ch3map a26 n/a (1) 6.12.14 comparator_e the primary function of the comparator_e module is to support precision slope analog-to-digital conversions, battery voltage supervision, and monitoring of external analog signals. see table 6-78 for control and configuration registers. 6.12.15 crc16 the crc16 module produces a signature based on a sequence of entered data values and can be used for data checking purposes. the crc16 module signature is based on the crc-ccitt standard. see table 6-46 for control and configuration registers. 6.12.16 crc32 the crc32 module produces a signature based on a sequence of entered data values and can be used for data checking purposes. the crc32 signature is based on the iso 3309 standard. see table 6-79 for control and configuration registers.
82 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.12.17 aes256 accelerator the aes accelerator module performs encryption and decryption of 128-bit data with 128-, 192-, or 256- bit keys according to the advanced encryption standard (aes) (fips pub 197) in hardware. see table 6- 80 for control and configuration registers. 6.12.18 true random seed the device descriptor information (tlv) section contains a 128-bit true random seed that can be used to implement a deterministic random number generator. 6.12.19 shared reference (ref) the ref module generates all critical reference voltages that can be used by the various analog peripherals in the device. 6.12.20 embedded emulation 6.12.20.1 embedded emulation module (eem) (s version) the eem supports real-time in-system debugging. the s version of the eem has the following features: ? three hardware triggers or breakpoints on memory access ? one hardware trigger or breakpoint on cpu register write access ? up to four hardware triggers can be combined to form complex triggers or breakpoints ? one cycle counter ? clock control on module level 6.12.20.2 energytrace++ ? technology the devices implement circuitry to support energytrace++ technology. the energytrace++ technology allows you to observe information about the internal states of the microcontroller. these states include the cpu program counter (pc), the on or off status of the peripherals and the system clocks (regardless of the clock source), and the low-power mode currently in use. these states can always be read by a debug tool, even when the microcontroller sleeps in lpmx.5 modes. the activity of the following modules can be observed: ? lea is running (msp430fr599x only). ? mpy is calculating. ? wdt is counting. ? rtc is counting. ? adc: a sequence, sample, or conversion is active. ? ref: refbg or refgen active and bg in static mode. ? comp is on. ? aes is encrypting or decrypting. ? eusci_a0 is transferring (receiving or transmitting) data. ? eusci_a1 is transferring (receiving or transmitting) data. ? eusci_a2 is transferring (receiving or transmitting) data. ? eusci_a3 is transferring (receiving or transmitting) data. ? eusci_b0 is transferring (receiving or transmitting) data. ? eusci_b1 is transferring (receiving or transmitting) data. ? eusci_b2 is transferring (receiving or transmitting) data. ? eusci_b3 is transferring (receiving or transmitting) data. ? tb0 is counting. ? ta0 is counting.
83 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated ? ta1 is counting. ? ta2 is counting. ? ta3 is counting. ? ta4 is counting.
84 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.13 input/output diagrams 6.13.1 capacitive touch functionality on ports p1 to p8, and pj all port pins provide the capacitive touch functionality (see figure 6-2 ). the capacitive touch functionality is controlled using the capacitive touch i/o control registers captio0ctl and captio1ctl as described in the msp430fr58xx, msp430fr59xx, msp430fr68xx, msp430fr69xx family user ' s guide . the capacitive touch functionality is not shown in the individual pin schematics in the following sections. note: functional representation only. figure 6-2. capacitive touch functionality on ports 01 01 1 pxren.y pxout.y direction control analog enable capacitive touch enable 0 output signal dvss dvcc input signal px.y capacitive touch signal 0 capacitive touch signal 1 en d q capacitive touch enable 1
85 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.13.2 port p1 (p1.0 to p1.2) input/output with schmitt trigger figure 6-3 shows the port diagram. table 6-20 summarizes the selection of the pin functions. note: functional representation only. figure 6-3. port p1 (p1.0 to p1.2) diagram p1.0/ta0.1/dmae0/rtcclk/ a0/c0/vref-/veref- p1.1/ta0.2/ta1clk/cout/ a1/c1vref+/veref+ p1.2/ta1.1/ta0clk/cout/a2/c2 p1sel1.x p1dir.x p1in.x en to modules from module 1 p1out.x 1 0 dvssdvcc 1 d to comparator from comparator pad logic to adc from adc bus keeper direction0: input 1: output cbpd.x p1ren.x 0 1 0 01 0 1 1 p1sel0.x 0 1 0 01 0 1 1 from module 2 (adc) reference (p1.0, p1.1) dvss
86 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated (1) x = don ' t care (2) do not use this pin as rtcclk output if the dmae0 functionality is used on any other pin. select an alternate rtcclk output pin. (3) setting p1sel1.x and p1sel0.x disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. (4) setting the cepdx bit of the comparator disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. selecting the cx input pin to the comparator multiplexer with the input select bits in the comparator module automatically disables output driver and input buffer for that pin, regardless of the state of the associated cepdx bit. (5) do not use this pin as cout output if the ta1clk functionality is used on any other pin. select an alternate cout output pin. table 6-20. port p1 (p1.0 to p1.2) pin functions pin name (p1.x) x function control bits and signals (1) p1dir.x p1sel1.x p1sel0.x p1.0/ta0.1/dmae0/rtcclk/a0/c0/ vref-/veref- 0 p1.0 (i/o) i: 0; o: 1 0 0 ta0.cci1a 0 0 1 ta0.1 1 dmae0 0 1 0 rtcclk (2) 1 a0, c0, vref-, veref- (3) (4) x 1 1 p1.1/ta0.2/ta1clk/cout/a1/c1/ vref+/veref+ 1 p1.1 (i/o) i: 0; o: 1 0 0 ta0.cci2a 0 0 1 ta0.2 1 ta1clk 0 1 0 cout (5) 1 a1, c1, vref+, veref+ (3) (4) x 1 1 p1.2/ta1.1/ta0clk/cout/a2/c2 2 p1.2 (i/o) i: 0; o: 1 0 0 ta1.cci1a 0 0 1 ta1.1 1 ta0clk 0 1 0 cout (5) 1 a2, c2 (3) (4) x 1 1
87 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.13.3 port p1 (p1.3 to p1.5) input/output with schmitt trigger figure 6-4 shows the port diagram. table 6-21 summarizes the selection of the pin functions. note: functional representation only. figure 6-4. port p1 (p1.3 to p1.5) diagram p1.3/ta1.2/ucb0ste/a3/c3 p1.4/tb0.1/uca0ste/a4/c4 p1.5/tb0.2/uca0clk/a5/c5 p1sel1.x p1dir.x p1in.x en to modules from module 1 p1out.x 1 0 dvssdvcc 1 d to comparator from comparator pad logic to adc from adc bus keeper direction0: input 1: output cbpd.x p1ren.x 0 1 0 01 0 1 1 p1sel0.x 0 1 0 01 0 1 1 from module 2 from module 2 dvss
88 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated (1) x = don ' t care (2) direction controlled by eusci_b0 module. (3) setting p1sel1.x and p1sel0.x disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. (4) setting the cepdx bit of the comparator disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. selecting the cx input pin to the comparator multiplexer with the input select bits in the comparator module automatically disables output driver and input buffer for that pin, regardless of the state of the associated cepdx bit. (5) direction controlled by eusci_a0 module. table 6-21. port p1 (p1.3 to p1.5) pin functions pin name (p1.x) x function control bits and signals (1) p1dir.x p1sel1.x p1sel0.x p1.3/ta1.2/ucb0ste/a3/c3 3 p1.3 (i/o) i: 0; o: 1 0 0 ta1.cci2a 0 0 1 ta1.2 1 ucb0ste x (2) 1 0 a3, c3 (3) (4) x 1 1 p1.4/tb0.1/uca0ste/a4/c4 4 p1.4 (i/o) i: 0; o: 1 0 0 tb0.cci1a 0 0 1 tb0.1 1 uca0ste x (5) 1 0 a4, c4 (3) (4) x 1 1 p1.5/tb0.2/uca0clk/a5/c5 5 p1.5(i/o) i: 0; o: 1 0 0 tb0.cci2a 0 0 1 tb0.2 1 uca0clk x (5) 1 0 a5, c5 (3) (4) x 1 1
89 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated (1) x = don ' t care (2) direction controlled by eusci_b0 module. (3) direction controlled by eusci_a0 module. 6.13.4 port p1 (p1.6 and p1.7) input/output with schmitt trigger figure 6-5 shows the port diagram. table 6-22 summarizes the selection of the pin functions. note: functional representation only. figure 6-5. port p1 (p1.6 and p1.7) diagram table 6-22. port p1 (p1.6 and p1.7) pin functions pin name (p1.x) x function control bits and signals (1) p1dir.x p1sel1.x p1sel0.x p1.6/tb0.3/ucb0simo/ucb0sda/ ta0.0 6 p1.6 (i/o) i: 0; o: 1 0 0 tb0.cci3b 0 0 1 tb0.3 1 ucb0simo/ucb0sda x (2) 1 0 ta0.cci0a 0 1 1 ta0.0 1 p1.7/tb0.4/ucb0somi/ucb0scl/ ta1.0 7 p1.7 (i/o) i: 0; o: 1 0 0 tb0.cci4b 0 0 1 tb0.4 1 ucb0somi/ucb0scl x (3) 1 0 ta1.cci0a 0 1 1 ta1.0 1 p1.6/tb0.3/ucb0simo/ucb0sda/ta0.0 p1.7/tb0.4/ucb0somi/ucb0scl/ta1.0 p1sel1.x p1dir.x p1in.x en to modules from module 1 p1out.x 1 0 dvssdvcc 1 d pad logic direction0: input 1: output p1ren.x 0 1 0 01 0 1 1 p1sel0.x 0 1 0 01 0 1 1 from module 2 from module 2 from module 3
90 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.13.5 port p2 (p2.0 to p2.2) input/output with schmitt trigger figure 6-6 shows the port diagram. table 6-23 summarizes the selection of the pin functions. note: functional representation only. figure 6-6. port p2 (p2.0 to p2.2) diagram p2.0/tb0.6/uca0txd/uca0simo/ tb0clk/aclk p2.1/tb0.0/uca0rxd/uca0somi/ tb0.0 p2.2/tb0.2/ucb0clk p2sel1.x p2dir.x p2in.x en to modules from module 1 p2out.x 1 0 dvssdvcc 1 d pad logic direction0: input 1: output p2ren.x 0 1 0 01 0 1 1 p2sel0.x 0 1 0 01 0 1 1 from module 2 from module 2 from module 3
91 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated (1) x = don ' t care (2) direction controlled by eusci_a0 module. (3) do not use this pin as aclk output if the tb0clk functionality is used on any other pin. select an alternate aclk output pin. (4) direction controlled by eusci_b0 module. table 6-23. port p2 (p2.0 to p2.2) pin functions pin name (p2.x) x function control bits and signals (1) p2dir.x p2sel1.x p2sel0.x p2.0/tb0.6/uca0txd/uca0simo/ tb0clk/aclk 0 p2.0 (i/o) i: 0; o: 1 0 0 tb0.cci6b 0 0 1 tb0.6 1 uca0txd/uca0simo x (2) 1 0 tb0clk 0 1 1 aclk (3) 1 p2.1/tb0.0/uca0rxd/uca0somi 1 p2.1 (i/o) i: 0; o: 1 0 0 tb0.cci0a 0 x 1 tb0.0 1 uca0rxd/uca0somi x (2) 1 0 p2.2/tb0.2/ucb0clk 2 p2.2 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 tb0.2 1 ucb0clk x (4) 1 0 n/a 0 1 1 internally tied to dvss 1
92 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.13.6 port p2 (p2.3 and p2.4) input/output with schmitt trigger figure 6-7 shows the port diagram. table 6-24 summarizes the selection of the pin functions. note: functional representation only. figure 6-7. port p2 (p2.3 and p2.4) diagram p2.3/ta0.0/uca1ste/a6/c10 p2.4/ta1.0/uca1clk/a7/c11 p2sel1.x p2dir.x p2in.x en to modules from module 1 p2out.x 1 0 dvssdvcc 1 d to comparator from comparator pad logic to adc from adc bus keeper direction0: input 1: output cbpd.x p2ren.x 0 1 0 01 0 1 1 p2sel0.x 0 1 0 01 0 1 1 from module 2 from module 2 dvss
93 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated (1) x = don ' t care (2) direction controlled by eusci_a1 module. (3) setting p2sel1.x and p2sel0.x disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. (4) setting the cepdx bit of the comparator disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. selecting the cx input pin to the comparator multiplexer with the input select bits in the comparator module automatically disables output driver and input buffer for that pin, regardless of the state of the associated cepdx bit. table 6-24. port p2 (p2.3 and p2.4) pin functions pin name (p2.x) x function control bits and signals (1) p2dir.x p2sel1.x p2sel0.x p2.3/ta0.0/uca1ste/a6/c10 3 p2.3 (i/o) i: 0; o: 1 0 0 ta0.cci0b 0 0 1 ta0.0 1 uca1ste x (2) 1 0 a6, c10 (3) (4) x 1 1 p2.4/ta1.0/uca1clk/a7/c11 4 p2.4 (i/o) i: 0; o: 1 0 0 ta1.cci0b 0 0 1 ta1.0 1 uca1clk x (2) 1 0 a7, c11 (3) (4) x 1 1
94 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated (1) x = don ' t care (2) direction controlled by eusci_a1 module. 6.13.7 port p2 (p2.5 and p2.6) input/output with schmitt trigger figure 6-8 shows the port diagram. table 6-25 summarizes the selection of the pin functions. note: functional representation only. figure 6-8. port p2 (p2.5 and p2.6) diagram table 6-25. port p2 (p2.5 and p2.6) pin functions pin name (p2.x) x function control bits and signals (1) p2dir.x p2sel1.x p2sel0.x p2.5/tb0.0/uca1txd/uca1simo 5 p2.5(i/o) i: 0; o: 1 0 0 tb0.cci0b 0 0 1 tb0.0 1 uca1txd/uca1simo x (2) 1 0 n/a 0 1 1 internally tied to dvss 1 p2.6/tb0.1/uca1rxd/uca1somi 6 p2.6(i/o) i: 0; o: 1 0 0 n/a 0 0 1 tb0.1 1 uca1rxd/uca1somi x (2) 1 0 n/a 0 1 1 internally tied to dvss 1 p2.5/tb0.0/uca1txd/uca1simop2.6/tb0.1/uca1rxd/uca1somi p2sel1.x p2dir.x p2in.x en to modules from module 1 p2out.x 1 0 dvssdvcc 1 d pad logic direction0: input 1: output p2ren.x 0 1 0 01 0 1 1 p2sel0.x 0 1 0 01 0 1 1 from module 2 from module 2 dvss
95 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated (1) x = don ' t care 6.13.8 port p2 (p2.7) input/output with schmitt trigger figure 6-9 shows the port diagram. table 6-26 summarizes the selection of the pin functions. note: functional representation only. figure 6-9. port p2 (p2.7) diagram table 6-26. port p2 (p2.7) pin functions pin name (p2.x) x function control bits and signals (1) p2dir.x p2sel1.x p2sel0.x p2.7 7 p2.7(i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 x internally tied to dvss 1 p2.7 p2sel1.x p2dir.x p2in.x en to modules p2out.x 1 0 dvssdvcc 1 d pad logic bus keeper direction0: input 1: output p2ren.x 0 1 0 01 0 1 1 p2sel0.x 0 1 0 01 0 1 1 dvssdvss dvss
96 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.13.9 port p3 (p3.0 to p3.3) input/output with schmitt trigger figure 6-10 shows the port diagram. table 6-27 summarizes the selection of the pin functions. note: functional representation only. figure 6-10. port p3 (p3.0 to p3.3) diagram p3.0/a12/c12p3.1/a13/c13 p3.2/a14/c14 p3.3/a15/c15 p3sel1.x p3dir.x p3in.x en to modules dvss p3out.x 1 0 dvssdvcc 1 d to comparator from comparator pad logic to adc from adc bus keeper direction0: input 1: output cbpd.x p3ren.x 0 1 0 01 0 1 1 p3sel0.x 0 1 0 01 0 1 1 dvssdvss
97 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated (1) x = don ' t care (2) setting p3sel1.x and p3sel0.x disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. (3) setting the cepdx bit of the comparator disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. selecting the cx input pin to the comparator multiplexer with the input select bits in the comparator module automatically disables output driver and input buffer for that pin, regardless of the state of the associated cepdx bit. table 6-27. port p3 (p3.0 to p3.3) pin functions pin name (p3.x) x function control bits and signals (1) p3dir.x p3sel1.x p3sel0.x p3.0/a12/c12 0 p3.0 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 0 internally tied to dvss 1 a12/c12 (2) (3) x 1 1 p3.1/a13/c13 1 p3.1 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 0 internally tied to dvss 1 a13/c13 (2) (3) x 1 1 p3.2/a14/c14 2 p3.2 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 0 internally tied to dvss 1 a14/c14 (2) (3) x 1 1 p3.3/a15/c15 3 p3.3 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 0 internally tied to dvss 1 a15/c15 (2) (3) x 1 1
98 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.13.10 port p3 (p3.4 to p3.7) input/output with schmitt trigger figure 6-11 shows the port diagram. table 6-28 summarizes the selection of the pin functions. note: functional representation only. figure 6-11. port p3 (p3.4 to p3.7) diagram p3.4/tb0.3/smclkp3.5/tb0.4/cbout p3.6/tb0.5 p3.7/tb0.6 p3sel1.x p3dir.x p3in.x en to modules from module 1 p3out.x 1 0 dvssdvcc 1 d pad logic direction0: input 1: output p3ren.x 0 1 0 01 0 1 1 p3sel0.x 0 1 0 01 0 1 1 from module 2 from module 3
99 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated (1) x = don ' t care table 6-28. port p3 (p3.4 to p3.7) pin functions pin name (p3.x) x function control bits and signals (1) p3dir.x p3sel1.x p3sel0.x p3.4/tb0.3/smclk 4 p3.4 (i/o) i: 0; o: 1 0 0 tb0.cci3a 0 0 1 tb0.3 1 n/a 0 1 x smclk 1 p3.5/tb0.4/cout 5 p3.5 (i/o) i: 0; o: 1 0 0 tb0.cci4a 0 0 1 tb0.4 1 n/a 0 1 x cout 1 p3.6/tb0.5 6 p3.6 (i/o) i: 0; o: 1 0 0 tb0.cci5a 0 0 1 tb0.5 1 n/a 0 1 x internally tied to dvss 1 p3.7/tb0.6 7 p3.7 (i/o) i: 0; o: 1 0 0 tb0.cci6a 0 0 1 tb0.6 1 n/a 0 1 x internally tied to dvss 1
100 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.13.11 port p4 (p4.0 to p4.3) input/output with schmitt trigger figure 6-12 shows the port diagram. table 6-29 summarizes the selection of the pin functions. note: functional representation only. figure 6-12. port p4 (p4.0 to p4.3) diagram p4.0/a8p4.1/a9 p4.2/a10 p4.3/a11 p4sel1.x p4dir.x p4in.x en to modules dvss p4out.x 1 0 dvssdvcc 1 d pad logic to adc from adc bus keeper direction0: input 1: output p4ren.x 0 1 0 01 0 1 1 p4sel0.x 0 1 0 01 0 1 1 dvssdvss
101 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated (1) x = don ' t care (2) setting p4sel1.x and p4sel0.x disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. table 6-29. port p4 (p4.0 to p4.3) pin functions pin name (p4.x) x function control bits and signals (1) p4dir.x p4sel1.x p4sel0.x p4.0/a8 0 p4.0 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 0 internally tied to dvss 1 a8 (2) x 1 1 p4.1/a9 1 p4.1 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 0 internally tied to dvss 1 a9 (2) x 1 1 p4.2/a10 2 p4.2 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 0 internally tied to dvss 1 a10 (2) x 1 1 p4.3/a11 3 p4.3 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 0 internally tied to dvss 1 a11 (2) x 1 1
102 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.13.12 port p4 (p4.4 to p4.7) input/output with schmitt trigger figure 6-13 shows the port diagram. table 6-30 summarizes the selection of the pin functions. note: functional representation only. figure 6-13. port p4 (p4.4 to p4.7) diagram p4.4/tb0.5p4.5 p4.6 p4.7 p4sel1.x p4dir.x p4in.x en to modules from module 1 p4out.x 1 0 dvssdvcc 1 d pad logic direction0: input 1: output p4ren.x 0 1 0 01 0 1 1 p4sel0.x 0 1 0 01 0 1 1 dvss dvss
103 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated (1) x = don ' t care table 6-30. port p4 (p4.4 to p4.7) pin functions pin name (p4.x) x function control bits and signals (1) p4dir.x p4sel1.x p4sel0.x p4.4/tb0.5 4 p4.4 (i/o) i: 0; o: 1 0 0 tb0.cci5b 0 0 1 tb0.5 1 n/a 0 1 x internally tied to dvss 1 p4.5 5 p4.5 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 x internally tied to dvss 1 p4.6 6 p4.6 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 x internally tied to dvss 1 p4.7 7 p4.7 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 x internally tied to dvss 1
104 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.13.13 port p5 (p5.0 to p5.7) input/output with schmitt trigger figure 6-14 shows the port diagram. table 6-31 summarizes the selection of the pin functions. note: functional representation only. figure 6-14. port p5 (p5.0 to p5.7) diagram p5.0/ucb1simo/ucb1sdap5.1/ucb1somi/ucb1scl p5.2/ucb1clk/ta4clk p5.3/ucb1ste p5.4/uca2txd/uca2simo/tb0outh p5.5/uca2rxd/uca2somi/aclk p5.6/uca2clk/ta4.0/smclk p5.7/uca2ste/ta4.1/mclk p5sel1.x p5dir.x p5in.x en to modules from module 1 p5out.x 1 0 dvssdvcc 1 d pad logic direction0: input 1: output p5ren.x 0 1 0 01 0 1 1 p5sel0.x 0 1 0 01 0 1 1 dvss dvss
105 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated (1) x = don ' t care (2) direction controlled by eusci_b0 module. (3) direction controlled by eusci_a2 module. table 6-31. port p5 (p5.0 to p5.7) pin functions pin name (p5.x) x function control bits and signals (1) p5dir.x p5sel1.x p5sel0.x p5.0/ucb1simo/ucb1sda 0 p5.0 (i/o) i: 0; o: 1 0 0 ucb1simo/ucb1sda x (2) 0 1 n/a 0 1 x internally tied to dvss 1 p5.1/ucb1somi/ucb1scl 1 p5.1 (i/o) i: 0; o: 1 0 0 ucb1somi/ucb1scl x (2) 0 1 n/a 0 1 x internally tied to dvss 1 p5.2/ucb1clk/ta4clk 2 p5.2 (i/o) i: 0; o: 1 0 0 ucb1clk x (2) 0 1 ta4clk 0 1 0 internally tied to dvss 1 n/a 0 1 1 internally tied to dvss 1 p5.3/ucb1ste 3 p5.3 (i/o) i: 0; o: 1 0 0 ucb1ste x (2) 0 1 n/a 0 1 1 internally tied to dvss 1 p5.4/uca2txd/uca2simo/tb 0outh 4 p5.4 (i/o) i: 0; o: 1 0 0 uca2txd/uca2simo x (3) 0 1 n/a 0 1 0 internally tied to dvss 1 tb0outh 0 1 1 internally tied to dvss 1 p5.5/uca2rxd/uca2somi/ac lk 5 p5.5 (i/o) i: 0; o: 1 0 0 uca2rxd/uca2somi x (3) 0 1 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 1 aclk 1 p5.6/uca2clk/ta4.0/smclk 6 p5.6 (i/o) i: 0; o: 1 0 0 uca2clk x (3) 0 1 ta4.cci0a 0 1 0 ta4.0 1 n/a 0 1 1 smclk 1 p5.7/uca2ste/ta4.1/mclk 7 p5.7 (i/o) i: 0; o: 1 0 0 uca2ste x (3) 0 1 ta4.cci1a 0 1 0 ta4.1 1 na 0 1 1 mclk 1
106 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.13.14 port p6 (p6.0 to p6.7) input/output with schmitt trigger figure 6-15 shows the port diagram. table 6-32 summarizes the selection of the pin functions. note: functional representation only. figure 6-15. port p6 (p6.0 to p6.7) diagram p6.0/uca3txd/uca3simop6.1/uca3rxd/uca3somi p6.2/uca3clk p6.3/uca3ste p6.4/ucb3simo/ucb3sda p6.5/ucb3somi/ucb3scl p6.6/ucb3clk p6.7/ucb3ste p6sel1.x p6dir.x p6in.x en to modules from module 1 p6out.x 1 0 dvssdvcc 1 d pad logic direction0: input 1: output p6ren.x 0 1 0 01 0 1 1 p6sel0.x 0 1 0 01 0 1 1 dvss dvss
107 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated (1) x = don ' t care (2) direction controlled by eusci_a3 module. (3) direction controlled by eusci_b3 module. table 6-32. port p6 (p6.0 to p6.7) pin functions pin name (p6.x) x function control bits and signals (1) p6dir.x p6sel1.x p6sel0.x p6.0/uca3txd/uca3simo 0 p6.0 (i/o) i: 0; o: 1 0 0 uca3txd/uca3simo x (2) 0 1 n/a 0 1 x internally tied to dvss 1 p6.1/uca3rxd/uca3somi 1 p6.1 (i/o) i: 0; o: 1 0 0 uca3rxd/uca3somi x (2) 0 1 n/a 0 1 x internally tied to dvss 1 p6.2/uca3clk 2 p6.2 (i/o) i: 0; o: 1 0 0 uca3clk x (2) 0 1 n/a 0 1 x internally tied to dvss 1 p6.3/uca3ste 3 p6.3 (i/o) i: 0; o: 1 0 0 uca3ste x (2) 0 1 n/a 0 1 x internally tied to dvss 1 p6.4/ucb3simo/ucb3sda 4 p6.4 (i/o) i: 0; o: 1 0 0 ucb3simo/ucb3sda x (3) 0 1 n/a 0 1 x internally tied to dvss 1 p6.5/ucb3somi/ucb3scl 5 p6.5 (i/o) i: 0; o: 1 0 0 ucb3somi/ucb3scl x (3) 0 1 n/a 0 0 x internally tied to dvss 1 p6.6/ucb3clk 6 p6.6 (i/o) i: 0; o: 1 0 0 ucb3clk x (3) 0 1 n/a 0 0 x internally tied to dvss 1 p6.7/ucb3ste 7 p6.7 (i/o) i: 0; o: 1 0 0 ucb3ste x (3) 0 1 n/a 0 0 x internally tied to dvss 1
108 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.13.15 port p7 (p7.0 to p7.3) input/output with schmitt trigger figure 6-16 shows the port diagram. table 6-33 summarizes the selection of the pin functions. note: functional representation only. figure 6-16. port p7 (p7.0 to p7.3) diagram p7.0/ucb2simo/ucb2sdap7.1/ucb2somi/ucb2scl p7.2/ucb2clk p7.3/ucb2ste/ta4.1 p7sel1.x p7dir.x p7in.x en to modules from module 1 p7out.x 1 0 dvssdvcc 1 d pad logic direction0: input 1: output p7ren.x 0 1 0 01 0 1 1 p7sel0.x 0 1 0 01 0 1 1 dvss dvss
109 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated (1) x = don ' t care (2) direction controlled by eusci_b2 module. table 6-33. port p7 (p7.0 to p7.3) pin functions pin name (p7.x) x function control bits and signals (1) p7dir.x p7sel1.x p7sel0.x p7.0/ucb2simo/ucb2sda 0 p7.0 (i/o) i: 0; o: 1 0 0 ucb2simo/ucb2sda x (2) 0 1 n/a 0 1 x internally tied to dvss 1 p7.1/ucb2somi/ucb2scl 1 p7.1 (i/o) i: 0; o: 1 0 0 ucb2somi/ucb2scl x (2) 0 1 n/a 0 1 x internally tied to dvss 1 p7.2/ucb2clk 2 p7.2 (i/o) i: 0; o: 1 0 0 ucb2clk x (2) 0 1 n/a 0 1 x internally tied to dvss 1 p7.3/ucb2ste/ta4.1 3 p7.3 (i/o) i: 0; o: 1 0 0 ucb2ste x (2) 0 1 ta4.cci1b 0 1 0 ta4.1 1 n/a 0 1 1 internally tied to dvss 1
110 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.13.16 port p7 (p7.4 to p7.7) input/output with schmitt trigger figure 6-17 shows the port diagram. table 6-34 summarizes the selection of the pin functions. note: functional representation only. figure 6-17. port p7 (p7.3 to p7.7) diagram p7.4/ta4.0/a16 p7.5/a17 p7.6/a18 p7.7/a19 p7sel1.x p7dir.x p4in.x en to modules dvss p7out.x 1 0 dvssdvcc 1 d pad logic to adc from adc bus keeper direction0: input 1: output p7ren.x 0 1 0 01 0 1 1 p7sel0.x 0 1 0 01 0 1 1 dvss dvss
111 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated (1) x = don ' t care (2) setting p7sel1.x and p7sel0.x disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. table 6-34. port p7 (p7.3 to p7.7) pin functions pin name (p7.x) x function control bits and signals (1) p7dir.x p7sel1.x p7sel0.x p7.4/ta4.0/a16 4 p7.4 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 ta4.cci0b 0 1 0 ta4.0 1 a16 (2) x 1 1 p7.5/a17 5 p7.5 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 0 internally tied to dvss 1 a17 (2) x 1 1 p7.6/a18 6 p7.6 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 0 internally tied to dvss 1 a18 (2) x 1 1 p7.7/a19 7 p7.7 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 0 internally tied to dvss 1 a19 (2) x 1 1
112 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.13.17 port p8 (p8.0 to p8.3) input/output with schmitt trigger figure 6-18 shows the port diagram. table 6-35 summarizes the selection of the pin functions. note: functional representation only. figure 6-18. port p8 (p8.0 to p8.3) diagram p8.0p8.1 p8.2 p8.3 p8sel1.x p8dir.x p8in.x en to modules from module 1 p8out.x 1 0 dvssdvcc 1 d pad logic direction0: input 1: output p8ren.x 0 1 0 01 0 1 1 p8sel0.x 0 1 0 01 0 1 1 dvss dvss
113 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated (1) x = don ' t care table 6-35. port p8 (p8.0 to p8.3) pin functions pin name (p8.x) x function control bits and signals (1) p8dir.x p8sel1.x p8sel0.x p8.0 0 p8.0(i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 x internally tied to dvss 1 p8.1 1 p8.1 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 x internally tied to dvss 1 p8.2 2 p8.2 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 x internally tied to dvss 1 p8.3 3 p8.3 (i/o) i: 0; o: 1 0 0 n/a 0 0 1 internally tied to dvss 1 n/a 0 1 x internally tied to dvss 1
114 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.13.18 port pj (pj.4 and pj.5) input/output with schmitt trigger figure 6-19 and figure 6-20 show the port diagrams. table 6-36 summarizes the selection of the pin functions. note: functional representation only. figure 6-19. port pj (pj.4) diagram pj.4/lfxin pjsel1.4 pjdir.4 pjin.4 en to modules dvss pjout.4 1 0 dvssdvcc 1 d to lfxt xin pad logic bus keeper direction0: input 1: output pjren.4 0 1 0 01 0 1 1 pjsel0.4 0 1 0 01 0 1 1 dvssdvss
115 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated note: functional representation only. figure 6-20. port pj (pj.5) diagram pj.5/lfxout pjsel1.5 pjdir.5 pjin.5 en to modules dvss pjout.5 1 0 dvssdvcc 1 d to lfxt xout pad logic bus keeper direction0: input 1: output pjren.5 0 1 0 01 0 1 1 pjsel0.5 0 1 0 01 0 1 1 dvssdvss pjsel1.4 pjsel0.4 lfxtbypass
116 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated (1) x = don ' t care (2) if pjsel1.4 = 0 and pjsel0.4 = 1, the general-purpose i/o is disabled. when lfxtbypass = 0, pj.4 and pj.5 are configured for crystal operation and pjsel1.5 and pjsel0.5 are don ' t care. when lfxtbypass = 1, pj.4 is configured for bypass operation and pj.5 is configured as general-purpose i/o. (3) when pj.4 is configured in bypass mode, pj.5 is configured as general-purpose i/o. (4) if pjsel0.5 = 1 or pjsel1.5 = 1, the general-purpose i/o functionality is disabled. no input function is available. configured as output, the pin is actively pulled to zero. table 6-36. port pj (pj.4 and pj.5) pin functions pin name (pj.x) x function control bits and signals (1) pjdir.x pjsel1.5 pjsel0.5 pjsel1.4 pjsel0.4 lfxt bypass pj.4/lfxin 4 pj.4 (i/o) i: 0; o: 1 x x 0 0 x n/a 0 x x 1 x x internally tied to dvss 1 lfxin crystal mode (2) x x x 0 1 0 lfxin bypass mode (2) x x x 0 1 1 pj.5/lfxout 5 pj.5 (i/o) i: 0; o: 1 0 0 0 0 0 1 x x x 1 (3) n/a 0 see (4) see (4) 0 0 0 1 x x x 1 (3) internally tied to dvss 1 see (4) see (4) 0 0 0 1 x x x 1 (3) lfxout crystal mode (2) x x x 0 1 0
117 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.13.19 port pj (pj.6 and pj.7) input/output with schmitt trigger figure 6-21 and figure 6-22 show the port diagrams. table 6-37 summarizes the selection of the pin functions. note: functional representation only. figure 6-21. port pj (pj.6) diagram pj.6/hfxin pjsel1.6 pjdir.6 pjin.6 en to modules dvss pjout.6 1 0 dvssdvcc 1 d to hfxt xin pad logic bus keeper direction0: input 1: output pjren.6 0 1 0 01 0 1 1 pjsel0.6 0 1 0 01 0 1 1 dvssdvss
118 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated note: functional representation only. figure 6-22. port pj (pj.7) diagram pj.7/hfxout pjsel1.7 pjdir.7 pjin.7 en to modules dvss pjout.7 1 0 dvssdvcc 1 d to hfxt xout pad logic bus keeper direction0: input 1: output pjren.7 0 1 0 01 0 1 1 pjsel0.7 0 1 0 01 0 1 1 dvssdvss pjsel1.6 hfxtbypass pjsel0.6
119 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated (1) x = don ' t care (2) setting pjsel1.6 = 0 and pjsel0.6 = 1 causes the general-purpose i/o to be disabled. when hfxtbypass = 0, pj.6 and pj.7 are configured for crystal operation and pjsel1.6 and pjsel0.7 are do not care. when hfxtbypass = 1, pj.6 is configured for bypass operation and pj.7 is configured as general-purpose i/o. (3) with pjsel0.7 = 1 or pjsel1.7 =1 the general-purpose i/o functionality is disabled. no input function is available. configured as output the pin is actively pulled to zero. (4) when pj.6 is configured in bypass mode, pj.7 is configured as general-purpose i/o. table 6-37. port pj (pj.6 and pj.7) pin functions pin name (pj.x) x function control bits and signals (1) pjdir.x pjsel1.7 pjsel0.7 pjsel1.6 pjsel0.6 hfxtbypass pj.6/hfxin 6 pj.6 (i/o) i: 0; o: 1 x x 0 0 x n/a 0 x x 1 x x internally tied to dvss 1 hfxin crystal mode (2) x x x 0 1 0 hfxin bypass mode (2) x x x 0 1 1 pj.7/hfxout 7 pj.7 (i/o) (3) i: 0; o: 1 0 0 0 0 0 1 x x x 1 (4) n/a 0 see (3) see (3) 0 0 0 1 x x x 1 (4) internally tied to dvss 1 see (3) see (3) 0 0 0 1 x x x 1 (4) hfxout crystal mode (2) x x x 0 1 0
120 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.13.20 port pj (pj.0 to pj.3) jtag pins tdo, tms, tck, tdi/tclk, input/output with schmitt trigger figure 6-23 shows the port diagram. table 6-38 summarizes the selection of the pin functions. note: functional representation only. figure 6-23. port pj (pj.0 to pj.3) diagram pj.0/tdo/tb0outh/smclk/ srscg1/c6 pj.1/tdi/tclk/mclk/ srscg0/c7 pj.2/tms/aclk/ sroscoff/c8 pj.3/tck/ srcpuoff/c9 pjsel1.x pjdir.x pjin.x en to modules and jtag from module 1 pjout.x 1 0 dvssdvcc 1 d pad logic bus keeper direction0: input 1: output pjren.x 0 1 0 01 0 1 1 pjsel0.x 0 1 0 01 0 1 1 from status register (sr) dvss 0 1 0 1 jtag enable from jtag from jtag to comparator from comparator cbpd.x
121 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated (1) x = don ' t care (2) default condition (3) the pin direction is controlled by the jtag module. jtag mode selection is made through the sys module or by the spy-bi-wire four- wire entry sequence. neither pjsel1.x and pjsel0.x nor cepdx bits have an effect in these cases. (4) do not use this pin as smclk output if the tb0outh functionality is used on any other pin. select an alternate smclk output pin. (5) setting the cepdx bit of the comparator disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. selecting the cx input pin to the comparator multiplexer with the input select bits in the comparator module automatically disables the output driver and input buffer for that pin, regardless of the state of the associated cepdx bit. (6) in jtag mode, pullups are activated automatically on tms, tck, and tdi/tclk. pjren.x are don ' t care. table 6-38. port pj (pj.0 to pj.3) pin functions pin name (pj.x) x function control bits or signals (1) pjdir.x pjsel1.x pjsel0.x cepdx (cx) pj.0/tdo/tb0outh/ smclk/srscg1/c6 0 pj.0 (i/o) (2) i: 0; o: 1 0 0 0 tdo (3) x x x 0 tb0outh 0 0 1 0 smclk (4) 1 n/a 0 1 0 0 cpu status register bit scg1 1 n/a 0 1 1 0 internally tied to dvss 1 c6 (5) x x x 1 pj.1/tdi/tclk/mclk/ srscg0/c7 1 pj.1 (i/o) (2) i: 0; o: 1 0 0 0 tdi/tclk (3) (6) x x x 0 n/a 0 0 1 0 mclk 1 n/a 0 1 0 0 cpu status register bit scg0 1 n/a 0 1 1 0 internally tied to dvss 1 c7 (5) x x x 1 pj.2/tms/aclk/ sroscoff/c8 2 pj.2 (i/o) (2) i: 0; o: 1 0 0 0 tms (3) (6) x x x 0 n/a 0 0 1 0 aclk 1 n/a 0 1 0 0 cpu status register bit oscoff 1 n/a 0 1 1 0 internally tied to dvss 1 c8 (5) x x x 1 pj.3/tck/srcpuoff/c9 3 pj.3 (i/o) (2) i: 0; o: 1 0 0 0 tck (3) (6) x x x 0 n/a 0 0 1 0 internally tied to dvss 1 n/a 0 1 0 0 cpu status register bit cpuoff 1 n/a 0 1 1 0 internally tied to dvss 1 c9 (5) x x x 1
122 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.14 device descriptors (tlv) table 6-40 lists the contents of the device descriptor tag-length-value (tlv) structure for msp430fr59xx(1) devices including aes. table 6-39 summarizes the device ids of the msp430fr59xx(1) devices. table 6-39. device ids device package device id 01a05h 01a04h msp430fr5994 zvw, pn, pm, and rgz 0x82 0xa1 msp430fr59941 zvw, pn, pm, and rgz 0x82 0xa2 msp430fr5992 zvw, pn, pm, and rgz 0x82 0xa3 msp430fr5964 zvw, pn, pm, and rgz 0x82 0xa4 msp430fr5962 zvw, pn, pm, and rgz 0x82 0xa6 (1) na = not applicable, per unit = content can differ among individual units table 6-40. device descriptor table msp430fr59xx(1) (1) description msp430fr59xx (uart bsl) msp430fr59941 (i 2 c bsl) address value address value info block info length 01a00h 06h 01a00h 06h crc length 01a01h 06h 01a01h 06h crc value 01a02h per unit 01a02h per unit 01a03h per unit 01a03h per unit device id 01a04h see table 6-39 . 01a04h see table 6-39 . 01a05h hardware revision 01a06h per unit 01a06h per unit firmware revision 01a07h per unit 01a07h per unit die record die record tag 01a08h 08h 01a08h 08h die record length 01a09h 0ah 01a09h 0ah lot/wafer id 01a0ah per unit 01a0ah per unit 01a0bh per unit 01a0bh per unit 01a0ch per unit 01a0ch per unit 01a0dh per unit 01a0dh per unit die x position 01a0eh per unit 01a0eh per unit 01a0fh per unit 01a0fh per unit die y position 01a10h per unit 01a10h per unit 01a11h per unit 01a11h per unit test results 01a12h per unit 01a12h per unit 01a13h per unit 01a13h per unit
123 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated table 6-40. device descriptor table msp430fr59xx(1) (1) (continued) description msp430fr59xx (uart bsl) msp430fr59941 (i 2 c bsl) address value address value (2) adc gain: the gain correction factor is measured at room temperature using a 2.5-v external voltage reference without internal buffer (adc12vrsel = 0x2, 0x4, or 0xe). other settings (for example, using internal reference) can result in different correction factors. (3) adc offset: the offset correction factor is measured at room temperature using adc12vrsel= 0x2 or 0x4, an external reference, v r+ = external 2.5 v, v r ? = avss. adc12 calibration adc12 calibration tag 01a14h 11h 01a14h 11h adc12 calibration length 01a15h 10h 01a15h 10h adc gain factor (2) 01a16h per unit 01a16h per unit 01a17h per unit 01a17h per unit adc offset (3) 01a18h per unit 01a18h per unit 01a19h per unit 01a19h per unit adc 1.2-v reference temperature sensor 30 c 01a1ah per unit 01a1ah per unit 01a1bh per unit 01a1bh per unit adc 1.2-v reference temperature sensor 85 c 01a1ch per unit 01a1ch per unit 01a1dh per unit 01a1dh per unit adc 2.0-v reference temperature sensor 30 c 01a1eh per unit 01a1eh per unit 01a1fh per unit 01a1fh per unit adc 2.0-v reference temperature sensor 85 c 01a20h per unit 01a20h per unit 01a21h per unit 01a21h per unit adc 2.5-v reference temperature sensor 30 c 01a22h per unit 01a22h per unit 01a23h per unit 01a23h per unit adc 2.5-v reference temperature sensor 85 c 01a24h per unit 01a24h per unit 01a25h per unit 01a25h per unit ref calibration ref calibration tag 01a26h 12h 01a26h 12h ref calibration length 01a27h 06h 01a27h 06h ref 1.2-v reference 01a28h per unit 01a28h per unit 01a29h per unit 01a29h per unit ref 2.0-v reference 01a2ah per unit 01a2ah per unit 01a2bh per unit 01a2bh per unit ref 2.5-v reference 01a2ch per unit 01a2ch per unit 01a2dh per unit 01a2dh per unit
124 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated table 6-40. device descriptor table msp430fr59xx(1) (1) (continued) description msp430fr59xx (uart bsl) msp430fr59941 (i 2 c bsl) address value address value (4) 128-bit random number: the random number is generated during production test using microsoft ' s cryptgenrandom() function. random number 128-bit random number tag 01a2eh 15h 01a2eh 15h random number length 01a2fh 10h 01a2fh 10h 128-bit random number (4) 01a30h per unit 01a30h per unit 01a31h per unit 01a31h per unit 01a32h per unit 01a32h per unit 01a33h per unit 01a33h per unit 01a34h per unit 01a34h per unit 01a35h per unit 01a35h per unit 01a36h per unit 01a36h per unit 01a37h per unit 01a37h per unit 01a38h per unit 01a38h per unit 01a39h per unit 01a39h per unit 01a3ah per unit 01a3ah per unit 01a3bh per unit 01a3bh per unit 01a3ch per unit 01a3ch per unit 01a3dh per unit 01a3dh per unit 01a3eh per unit 01a3eh per unit 01a3fh per unit 01a3fh per unit bsl configuration bsl tag 01a40h 1ch 01a40h 1ch bsl length 01a41h 02h 01a41h 02h bsl interface 01a42h 00h 01a42h 01h bsl interface configuration 01a43h 00h 01a43h 48h
125 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated (1) all address space not listed is considered vacant memory. 6.15 memory map table 6-41 summarizes the memory map for all device variants. table 6-41. memory organization (1) msp430fr5994, msp430fr5964 msp430fr5992, msp430fr5962 memory (fram) main: interrupt vectors and signatures main: code memory total size 256kb 00ffffh ? 00ff80h 043fffh ? 004000h 128kb 00ffffh ? 00ff80h 0023fffh ? 004000h ram (shared with lea on msp430fr599x) 4kb 003bffh ? 002c00h 4kb 003bffh ? 002c00h ram 4kb 002bffh ? 001c00h 4kb 002bffh ? 001c00h device descriptor (tlv) (fram) 256 b 001affh ? 001a00h 256 b 001affh ? 001a00h information memory (fram) info a 128 b 0019ffh ? 001980h 128 b 0019ffh ? 001980h info b 128 b 00197fh ? 001900h 128 b 00197fh ? 001900h info c 128 b 0018ffh ? 001880h 128 b 0018ffh ? 001880h info d 128 b 00187fh ? 001800h 128 b 00187fh ? 001800h bootloader (bsl) memory (rom) bsl 3 512 b 0017ffh ? 001600h 512 b 0017ffh ? 001600h bsl 2 512 b 0015ffh ? 001400h 512 b 0015ffh ? 001400h bsl 1 512 b 0013ffh ? 001200h 512 b 0013ffh ? 001200h bsl 0 512 b 0011ffh ? 001000h 512 b 0011ffh ? 001000h peripherals size 4kb 000fffh ? 000020h 4kb 000fffh ? 000020h tiny ram size 22 b 000001fh ? 00000ah 22 b 000001fh ? 00000ah reserved size 10 b 000009h ? 000000h 10 b 000009h ? 000000h
126 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.15.1 peripheral file map table 6-42 lists the base address and offset range for the supported module registers. for complete module register descriptions, see the msp430fr58xx, msp430fr59xx, msp430fr68xx, msp430fr69xx family user ' s guide . table 6-42. peripherals module name base address offset address range special functions (see table 6-43 ) 0100h 000h ? 01fh pmm (see table 6-44 ) 0120h 000h ? 01fh fram controller a (see table 6-45 ) 0140h 000h ? 00fh crc16 (see table 6-46 ) 0150h 000h ? 007h ram controller (see table 6-47 ) 0158h 000h ? 00fh watchdog (see table 6-48 ) 015ch 000h ? 001h cs (see table 6-49 ) 0160h 000h ? 00fh sys (see table 6-50 ) 0180h 000h ? 01fh shared reference (see table 6-51 ) 01b0h 000h ? 001h port p1, p2 (see table 6-52 ) 0200h 000h ? 01fh port p3, p4 (see table 6-53 ) 0220h 000h ? 01fh port p5, p6 (see table 6-54 ) 0240h 000h ? 01fh port p7, p8 (see table 6-55 ) 0260h 000h ? 01fh port pj (see table 6-56 ) 0320h 000h ? 01fh ta0 (see table 6-57 ) 0340h 000h ? 02fh ta1 (see table 6-58 ) 0380h 000h ? 02fh tb0 (see table 6-59 ) 03c0h 000h ? 02fh ta2 (see table 6-60 ) 0400h 000h ? 02fh capacitive touch i/o 0 (see table 6-61 ) 0430h 000h ? 00fh ta3 (see table 6-62 ) 0440h 000h ? 02fh capacitive touch i/o 1 (see table 6-63 ) 0470h 000h ? 00fh real-time clock (rtc_c) (see table 6-64 ) 04a0h 000h ? 01fh 32-bit hardware multiplier (see table 6-65 ) 04c0h 000h ? 02fh dma general control (see table 6-66 ) 0500h 000h ? 00fh dma channel 0 (see table 6-66 ) 0510h 000h ? 00fh dma channel 1 (see table 6-66 ) 0520h 000h ? 00fh dma channel 2 (see table 6-66 ) 0530h 000h ? 00fh dma channel 3 (see table 6-66 ) 0540h 000h ? 00fh dma channel 4 (see table 6-66 ) 0550h 000h ? 00fh dma channel 5 (see table 6-66 ) 0560h 000h ? 00fh mpu control (see table 6-67 ) 05a0h 000h ? 00fh eusci_a0 (see table 6-68 ) 05c0h 000h ? 01fh eusci_a1 (see table 6-69 ) 05e0h 000h ? 01fh eusci_a2 (see table 6-70 ) 0600h 000h ? 01fh eusci_a3 (see table 6-71 ) 0620h 000h ? 01fh eusci_b0 (see table 6-72 ) 0640h 000h ? 02fh eusci_b1 (see table 6-73 ) 0680h 000h ? 02fh eusci_b2 (see table 6-74 ) 06c0h 000h ? 02fh eusci_b3 (see table 6-75 ) 0700h 000h ? 02fh ta4 (see table 6-76 ) 07c0h 000h ? 02fh adc12_b (see table 6-77 ) 0800h 000h ? 09fh
127 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated table 6-42. peripherals (continued) module name base address offset address range (1) direct access to lea registers is not supported, and ti recommends using the optimized digital signal processing (dsp) library for msp microcontrollers for the operations that the lea module supports. comparator_e (see table 6-78 ) 08c0h 000h ? 00fh crc32 (see table 6-79 ) 0980h 000h ? 02fh aes (see table 6-80 ) 09c0h 000h ? 00fh lea (1) (msp430fr599x only) 0a80h 000h ? 07fh table 6-43. special function registers (base address: 0100h) register description acronym offset sfr interrupt enable sfrie1 00h sfr interrupt flag sfrifg1 02h sfr reset pin control sfrrpcr 04h table 6-44. pmm registers (base address: 0120h) register description acronym offset pmm control 0 pmmctl0 00h pmm interrupt flags pmmifg 0ah pm5 control 0 pm5ctl0 10h table 6-45. fram controller a (frctl_a) control registers (base address: 0140h) register description acronym offset fram control 0 frctl0 00h general control 0 gcctl0 04h general control 1 gcctl1 06h table 6-46. crc16 registers (base address: 0150h) register description acronym offset crc data input crc16di 00h crc data input reverse byte crcdirb 02h crc initialization and result crcinires 04h crc result reverse byte crcresr 06h table 6-47. ram controller registers (base address: 0158h) register description acronym offset ram controller control 0 rcctl0 00h table 6-48. watchdog registers (base address: 015ch) register description acronym offset watchdog timer control wdtctl 00h
128 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated table 6-49. cs registers (base address: 0160h) register description acronym offset cs control 0 csctl0 00h cs control 1 csctl1 02h cs control 2 csctl2 04h cs control 3 csctl3 06h cs control 4 csctl4 08h cs control 5 csctl5 0ah cs control 6 csctl6 0ch table 6-50. sys registers (base address: 0180h) register description acronym offset system control sysctl 00h jtag mailbox control sysjmbc 06h jtag mailbox input 0 sysjmbi0 08h jtag mailbox input 1 sysjmbi1 0ah jtag mailbox output 0 sysjmbo0 0ch jtag mailbox output 1 sysjmbo1 0eh user nmi vector generator sysuniv 1ah system nmi vector generator syssniv 1ch reset vector generator sysrstiv 1eh table 6-51. shared reference registers (base address: 01b0h) register description acronym offset shared reference control refctl 00h
129 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated table 6-52. port p1, p2 registers (base address: 0200h) register description acronym offset port p1 input p1in 00h port p1 output p1out 02h port p1 direction p1dir 04h port p1 resistor enable p1ren 06h port p1 selection 0 p1sel0 0ah port p1 selection 1 p1sel1 0ch port p1 interrupt vector word p1iv 0eh port p1 complement selection p1selc 16h port p1 interrupt edge select p1ies 18h port p1 interrupt enable p1ie 1ah port p1 interrupt flag p1ifg 1ch port p2 input p2in 01h port p2 output p2out 03h port p2 direction p2dir 05h port p2 resistor enable p2ren 07h port p2 selection 0 p2sel0 0bh port p2 selection 1 p2sel1 0dh port p2 complement selection p2selc 17h port p2 interrupt vector word p2iv 1eh port p2 interrupt edge select p2ies 19h port p2 interrupt enable p2ie 1bh port p2 interrupt flag p2ifg 1dh table 6-53. port p3, p4 registers (base address: 0220h) register description acronym offset port p3 input p3in 00h port p3 output p3out 02h port p3 direction p3dir 04h port p3 resistor enable p3ren 06h port p3 selection 0 p3sel0 0ah port p3 selection 1 p3sel1 0ch port p3 interrupt vector word p3iv 0eh port p3 complement selection p3selc 16h port p3 interrupt edge select p3ies 18h port p3 interrupt enable p3ie 1ah port p3 interrupt flag p3ifg 1ch port p4 input p4in 01h port p4 output p4out 03h port p4 direction p4dir 05h port p4 resistor enable p4ren 07h port p4 selection 0 p4sel0 0bh port p4 selection 1 p4sel1 0dh port p4 complement selection p4selc 17h port p4 interrupt vector word p4iv 1eh port p4 interrupt edge select p4ies 19h port p4 interrupt enable p4ie 1bh port p4 interrupt flag p4ifg 1dh
130 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated table 6-54. port p5, p6 registers (base address: 0240h) register description acronym offset port p5 input p5in 00h port p5 output p5out 02h port p5 direction p5dir 04h port p5 resistor enable p5ren 06h port p5 selection 0 p5sel0 0ah port p5 selection 1 p5sel1 0ch port p5 interrupt vector word p5iv 0eh port p5 complement selection p5selc 16h port p5 interrupt edge select p5ies 18h port p5 interrupt enable p5ie 1ah port p5 interrupt flag p5ifg 1ch port p6 input p6in 01h port p6 output p6out 03h port p6 direction p6dir 05h port p6 resistor enable p6ren 07h port p6 selection 0 p6sel0 0bh port p6 selection 1 p6sel1 0dh port p6 complement selection p6selc 17h port p6 interrupt vector word p6iv 1eh port p6 interrupt edge select p6ies 19h port p6 interrupt enable p6ie 1bh port p6 interrupt flag p6ifg 1dh table 6-55. port p7, p8 registers (base address: 0260h) register description acronym offset port p7 input p7in 00h port p7 output p7out 02h port p7 direction p7dir 04h port p7 resistor enable p7ren 06h port p7 selection 0 p7sel0 0ah port p7 selection 1 p7sel1 0ch port p7 interrupt vector word p7iv 0eh port p7 complement selection p7selc 16h port p7 interrupt edge select p7ies 18h port p7 interrupt enable p7ie 1ah port p7 interrupt flag p7ifg 1ch port p8 input p8in 01h port p8 output p8out 03h port p8 direction p8dir 05h port p8 resistor enable p8ren 07h port p8 selection 0 p8sel0 0bh port p8 selection 1 p8sel1 0dh port p8 complement selection p8selc 17h port p8 interrupt vector word p8iv 1eh port p8 interrupt edge select p8ies 19h port p8 interrupt enable p8ie 1bh port p8 interrupt flag p8ifg 1dh
131 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated table 6-56. port pj registers (base address: 0320h) register description acronym offset port pj input pjin 00h port pj output pjout 02h port pj direction pjdir 04h port pj resistor enable pjren 06h port pj selection 0 pjsel0 0ah port pj selection 1 pjsel1 0ch port pj complement selection pjselc 16h table 6-57. ta0 registers (base address: 0340h) register description acronym offset ta0 control ta0ctl 00h capture/compare control 0 ta0cctl0 02h capture/compare control 1 ta0cctl1 04h capture/compare control 2 ta0cctl2 06h ta0 counter ta0r 10h capture/compare 0 ta0ccr0 12h capture/compare 1 ta0ccr1 14h capture/compare 2 ta0ccr2 16h ta0 expansion 0 ta0ex0 20h ta0 interrupt vector ta0iv 2eh table 6-58. ta1 registers (base address: 0380h) register description acronym offset ta1 control ta1ctl 00h capture/compare control 0 ta1cctl0 02h capture/compare control 1 ta1cctl1 04h capture/compare control 2 ta1cctl2 06h ta1 counter ta1r 10h capture/compare 0 ta1ccr0 12h capture/compare 1 ta1ccr1 14h capture/compare 2 ta1ccr2 16h ta1 expansion 0 ta1ex0 20h ta1 interrupt vector ta1iv 2eh
132 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated table 6-59. tb0 registers (base address: 03c0h) register description acronym offset tb0 control tb0ctl 00h capture/compare control 0 tb0cctl0 02h capture/compare control 1 tb0cctl1 04h capture/compare control 2 tb0cctl2 06h capture/compare control 3 tb0cctl3 08h capture/compare control 4 tb0cctl4 0ah capture/compare control 5 tb0cctl5 0ch capture/compare control 6 tb0cctl6 0eh tb0 counter tb0r 10h capture/compare 0 tb0ccr0 12h capture/compare 1 tb0ccr1 14h capture/compare 2 tb0ccr2 16h capture/compare 3 tb0ccr3 18h capture/compare 4 tb0ccr4 1ah capture/compare 5 tb0ccr5 1ch capture/compare 6 tb0ccr6 1eh tb0 expansion 0 tb0ex0 20h tb0 interrupt vector tb0iv 2eh table 6-60. ta2 registers (base address: 0400h) register description acronym offset ta2 control ta2ctl 00h capture/compare control 0 ta2cctl0 02h capture/compare control 1 ta2cctl1 04h ta2 counter ta2r 10h capture/compare 0 ta2ccr0 12h capture/compare 1 ta2ccr1 14h ta2 expansion 0 ta2ex0 20h ta2 interrupt vector ta2iv 2eh table 6-61. capacitive touch i/o 0 registers (base address: 0430h) register description acronym offset capacitive touch i/o 0 control captio0ctl 0eh table 6-62. ta3 registers (base address: 0440h) register description acronym offset ta3 control ta3ctl 00h capture/compare control 0 ta3cctl0 02h capture/compare control 1 ta3cctl1 04h ta3 counter ta3r 10h capture/compare 0 ta3ccr0 12h capture/compare 1 ta3ccr1 14h ta3 expansion 0 ta3ex0 20h ta3 interrupt vector ta3iv 2eh
133 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated table 6-63. capacitive touch i/o 1 registers (base address: 0470h) register description acronym offset capacitive touch i/o 1 control captio1ctl 0eh table 6-64. rtc_c registers (base address: 04a0h) register description acronym offset rtc control 0 rtcctl0 00h rtc password rtcpwd 01h rtc control 1 rtcctl1 02h rtc control 3 rtcctl3 03h rtc offset calibration rtcocal 04h rtc temperature compensation rtctcmp 06h rtc prescaler 0 control rtcps0ctl 08h rtc prescaler 1 control rtcps1ctl 0ah rtc prescaler 0 rtcps0 0ch rtc prescaler 1 rtcps1 0dh rtc interrupt vector word rtciv 0eh rtc seconds/counter 1 rtcsec/rtcnt1 10h rtc minutes/counter 2 rtcmin/rtcnt2 11h rtc hours/counter 3 rtchour/rtcnt3 12h rtc day of week/counter 4 rtcdow/rtcnt4 13h rtc days rtcday 14h rtc month rtcmon 15h rtc year rtcyear 16h rtc alarm minutes rtcamin 18h rtc alarm hours rtcahour 19h rtc alarm day of week rtcadow 1ah rtc alarm days rtcaday 1bh binary-to-bcd conversion bin2bcd 1ch bcd-to-binary conversion bcd2bin 1eh
134 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated table 6-65. 32-bit hardware multiplier registers (base address: 04c0h) register description acronym offset 16-bit operand 1 ? multiply mpy 00h 16-bit operand 1 ? signed multiply mpys 02h 16-bit operand 1 ? multiply accumulate mac 04h 16-bit operand 1 ? signed multiply accumulate macs 06h 16-bit operand 2 op2 08h 16 16 result low word reslo 0ah 16 16 result high word reshi 0ch 16 16 sum extension sumext 0eh 32-bit operand 1 ? multiply low word mpy32l 10h 32-bit operand 1 ? multiply high word mpy32h 12h 32-bit operand 1 ? signed multiply low word mpys32l 14h 32-bit operand 1 ? signed multiply high word mpys32h 16h 32-bit operand 1 ? multiply accumulate low word mac32l 18h 32-bit operand 1 ? multiply accumulate high word mac32h 1ah 32-bit operand 1 ? signed multiply accumulate low word macs32l 1ch 32-bit operand 1 ? signed multiply accumulate high word macs32h 1eh 32-bit operand 2 ? low word op2l 20h 32-bit operand 2 ? high word op2h 22h 32 32 result 0 ? least significant word res0 24h 32 32 result 1 res1 26h 32 32 result 2 res2 28h 32 32 result 3 ? most significant word res3 2ah mpy32 control 0 mpy32ctl0 2ch
135 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated table 6-66. dma registers (base address dma general control: 0500h, channel 0: 0510h, channel 1: 0520h, channel 2: 0530h, channel 3: 0540h, channel 4: 0550h, channel 5: 0560h) register description acronym offset dma channel 0 control dma0ctl 00h dma channel 0 source address low dma0sal 02h dma channel 0 source address high dma0sah 04h dma channel 0 destination address low dma0dal 06h dma channel 0 destination address high dma0dah 08h dma channel 0 transfer size dma0sz 0ah dma channel 1 control dma1ctl 00h dma channel 1 source address low dma1sal 02h dma channel 1 source address high dma1sah 04h dma channel 1 destination address low dma1dal 06h dma channel 1 destination address high dma1dah 08h dma channel 1 transfer size dma1sz 0ah dma channel 2 control dma2ctl 00h dma channel 2 source address low dma2sal 02h dma channel 2 source address high dma2sah 04h dma channel 2 destination address low dma2dal 06h dma channel 2 destination address high dma2dah 08h dma channel 2 transfer size dma2sz 0ah dma channel 3 control dma3ctl 00h dma channel 3 source address low dma3sal 02h dma channel 3 source address high dma3sah 04h dma channel 3 destination address low dma3dal 06h dma channel 3 destination address high dma3dah 08h dma channel 3 transfer size dma3sz 0ah dma channel 4 control dma4ctl 00h dma channel 4 source address low dma4sal 02h dma channel 4 source address high dma4sah 04h dma channel 4 destination address low dma4dal 06h dma channel 4 destination address high dma4dah 08h dma channel 4 transfer size dma4sz 0ah dma channel 5 control dma5ctl 00h dma channel 5 source address low dma5sal 02h dma channel 5 source address high dma5sah 04h dma channel 5 destination address low dma5dal 06h dma channel 5 destination address high dma5dah 08h dma channel 5 transfer size dma5sz 0ah dma module control 0 dmactl0 00h dma module control 1 dmactl1 02h dma module control 2 dmactl2 04h dma module control 3 dmactl3 06h dma module control 4 dmactl4 08h dma interrupt vector dmaiv 0eh
136 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated table 6-67. mpu control registers (base address: 05a0h) register description acronym offset mpu control 0 mpuctl0 00h mpu control 1 mpuctl1 02h mpu segmentation border 2 mpusegb2 04h mpu segmentation border 1 mpusegb1 06h mpu access management mpusam 08h mpu ip control 0 mpuipc0 0ah mpu ip encapsulation segment border 2 mpuipsegb2 0ch mpu ip encapsulation segment border 1 mpuipsegb1 0eh table 6-68. eusci_a0 registers (base address: 05c0h) register description acronym offset eusci_a control word 0 uca0ctlw0 00h eusci _a control word 1 uca0ctlw1 02h eusci_a baud rate 0 uca0br0 06h eusci_a baud rate 1 uca0br1 07h eusci_a modulation control uca0mctlw 08h eusci_a status word uca0statw 0ah eusci_a receive buffer uca0rxbuf 0ch eusci_a transmit buffer uca0txbuf 0eh eusci_a lin control uca0abctl 10h eusci_a irda transmit control uca0irtctl 12h eusci_a irda receive control uca0irrctl 13h eusci_a interrupt enable uca0ie 1ah eusci_a interrupt flags uca0ifg 1ch eusci_a interrupt vector word uca0iv 1eh table 6-69. eusci_a1 registers (base address:05e0h) register description acronym offset eusci_a control word 0 uca1ctlw0 00h eusci _a control word 1 uca1ctlw1 02h eusci_a baud rate 0 uca1br0 06h eusci_a baud rate 1 uca1br1 07h eusci_a modulation control uca1mctlw 08h eusci_a status word uca1statw 0ah eusci_a receive buffer uca1rxbuf 0ch eusci_a transmit buffer uca1txbuf 0eh eusci_a lin control uca1abctl 10h eusci_a irda transmit control uca1irtctl 12h eusci_a irda receive control uca1irrctl 13h eusci_a interrupt enable uca1ie 1ah eusci_a interrupt flags uca1ifg 1ch eusci_a interrupt vector word uca1iv 1eh
137 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated table 6-70. eusci_a2 registers (base address:0600h) register description acronym offset eusci_a control word 0 uca2ctlw0 00h eusci _a control word 1 uca2ctlw1 02h eusci_a baud rate 0 uca2br0 06h eusci_a baud rate 1 uca2br1 07h eusci_a modulation control uca2mctlw 08h eusci_a status word uca2statw 0ah eusci_a receive buffer uca2rxbuf 0ch eusci_a transmit buffer uca2txbuf 0eh eusci_a lin control uca2abctl 10h eusci_a irda transmit control uca2irtctl 12h eusci_a irda receive control uca2irrctl 13h eusci_a interrupt enable uca2ie 1ah eusci_a interrupt flags uca2ifg 1ch eusci_a interrupt vector word uca2iv 1eh table 6-71. eusci_a3 registers (base address:0620h) register description acronym offset eusci_a control word 0 uca3ctlw0 00h eusci _a control word 1 uca3ctlw1 02h eusci_a baud rate 0 uca3br0 06h eusci_a baud rate 1 uca3br1 07h eusci_a modulation control uca3mctlw 08h eusci_a status word uca3statw 0ah eusci_a receive buffer uca3rxbuf 0ch eusci_a transmit buffer uca3txbuf 0eh eusci_a lin control uca3abctl 10h eusci_a irda transmit control uca3irtctl 12h eusci_a irda receive control uca3irrctl 13h eusci_a interrupt enable uca3ie 1ah eusci_a interrupt flags uca3ifg 1ch eusci_a interrupt vector word uca3iv 1eh
138 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated table 6-72. eusci_b0 registers (base address: 0640h) register description acronym offset eusci_b control word 0 ucb0ctlw0 00h eusci_b control word 1 ucb0ctlw1 02h eusci_b bit rate 0 ucb0br0 06h eusci_b bit rate 1 ucb0br1 07h eusci_b status word ucb0statw 08h eusci_b byte counter threshold ucb0tbcnt 0ah eusci_b receive buffer ucb0rxbuf 0ch eusci_b transmit buffer ucb0txbuf 0eh eusci_b i2c own address 0 ucb0i2coa0 14h eusci_b i2c own address 1 ucb0i2coa1 16h eusci_b i2c own address 2 ucb0i2coa2 18h eusci_b i2c own address 3 ucb0i2coa3 1ah eusci_b received address ucb0addrx 1ch eusci_b address mask ucb0addmask 1eh eusci i2c slave address ucb0i2csa 20h eusci interrupt enable ucb0ie 2ah eusci interrupt flags ucb0ifg 2ch eusci interrupt vector word ucb0iv 2eh table 6-73. eusci_b1 registers (base address: 0680h) register description acronym offset eusci_b control word 0 ucb1ctlw0 00h eusci_b control word 1 ucb1ctlw1 02h eusci_b bit rate 0 ucb1br0 06h eusci_b bit rate 1 ucb1br1 07h eusci_b status word ucb1statw 08h eusci_b byte counter threshold ucb1tbcnt 0ah eusci_b receive buffer ucb1rxbuf 0ch eusci_b transmit buffer ucb1txbuf 0eh eusci_b i2c own address 0 ucb1i2coa0 14h eusci_b i2c own address 1 ucb1i2coa1 16h eusci_b i2c own address 2 ucb1i2coa2 18h eusci_b i2c own address 3 ucb1i2coa3 1ah eusci_b received address ucb1addrx 1ch eusci_b address mask ucb1addmask 1eh eusci i2c slave address ucb1i2csa 20h eusci interrupt enable ucb1ie 2ah eusci interrupt flags ucb1ifg 2ch eusci interrupt vector word ucb1iv 2eh
139 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated table 6-74. eusci_b2 registers (base address: 06c0h) register description acronym offset eusci_b control word 0 ucb2ctlw0 00h eusci_b control word 1 ucb2ctlw1 02h eusci_b bit rate 0 ucb2br0 06h eusci_b bit rate 1 ucb2br1 07h eusci_b status word ucb2statw 08h eusci_b byte counter threshold ucb2tbcnt 0ah eusci_b receive buffer ucb2rxbuf 0ch eusci_b transmit buffer ucb2txbuf 0eh eusci_b i2c own address 0 ucb2i2coa0 14h eusci_b i2c own address 1 ucb2i2coa1 16h eusci_b i2c own address 2 ucb2i2coa2 18h eusci_b i2c own address 3 ucb2i2coa3 1ah eusci_b received address ucb2addrx 1ch eusci_b address mask ucb2addmask 1eh eusci i2c slave address ucb2i2csa 20h eusci interrupt enable ucb2ie 2ah eusci interrupt flags ucb2ifg 2ch eusci interrupt vector word ucb2iv 2eh table 6-75. eusci_b3 registers (base address: 0700h) register description acronym offset eusci_b control word 0 ucb3ctlw0 00h eusci_b control word 1 ucb3ctlw1 02h eusci_b bit rate 0 ucb3br0 06h eusci_b bit rate 1 ucb3br1 07h eusci_b status word ucb3statw 08h eusci_b byte counter threshold ucb3tbcnt 0ah eusci_b receive buffer ucb3rxbuf 0ch eusci_b transmit buffer ucb3txbuf 0eh eusci_b i2c own address 0 ucb3i2coa0 14h eusci_b i2c own address 1 ucb3i2coa1 16h eusci_b i2c own address 2 ucb3i2coa2 18h eusci_b i2c own address 3 ucb3i2coa3 1ah eusci_b received address ucb3addrx 1ch eusci_b address mask ucb3addmask 1eh eusci i2c slave address ucb3i2csa 20h eusci interrupt enable ucb3ie 2ah eusci interrupt flags ucb3ifg 2ch eusci interrupt vector word ucb3iv 2eh
140 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated table 6-76. ta4 registers (base address: 07c0h) register description acronym offset ta4 control ta4ctl 00h capture/compare control 0 ta4cctl0 02h capture/compare control 1 ta4cctl1 04h ta4 counter ta4r 10h capture/compare 0 ta4ccr0 12h capture/compare 1 ta4ccr1 14h ta4 expansion 0 ta4ex0 20h ta4 interrupt vector ta4iv 2eh table 6-77. adc12_b registers (base address: 0800h) register description acronym offset adc12_b control 0 adc12ctl0 00h adc12_b control 1 adc12ctl1 02h adc12_b control 2 adc12ctl2 04h adc12_b control 3 adc12ctl3 06h adc12_b window comparator low threshold register adc12lo 08h adc12_b window comparator high threshold register adc12hi 0ah adc12_b interrupt flag register 0 adc12ifgr0 0ch adc12_b interrupt flag register 1 adc12ifgr1 0eh adc12_b interrupt flag register 2 adc12ifgr2 10h adc12_b interrupt enable register 0 adc12ier0 12h adc12_b interrupt enable register 1 adc12ier1 14h adc12_b interrupt enable register 2 adc12ier2 16h adc12_b interrupt vector adc12iv 18h adc12_b memory control 0 adc12mctl0 20h adc12_b memory control 1 adc12mctl1 22h adc12_b memory control 2 adc12mctl2 24h adc12_b memory control 3 adc12mctl3 26h adc12_b memory control 4 adc12mctl4 28h adc12_b memory control 5 adc12mctl5 2ah adc12_b memory control 6 adc12mctl6 2ch adc12_b memory control 7 adc12mctl7 2eh adc12_b memory control 8 adc12mctl8 30h adc12_b memory control 9 adc12mctl9 32h adc12_b memory control 10 adc12mctl10 34h adc12_b memory control 11 adc12mctl11 36h adc12_b memory control 12 adc12mctl12 38h adc12_b memory control 13 adc12mctl13 3ah adc12_b memory control 14 adc12mctl14 3ch adc12_b memory control 15 adc12mctl15 3eh adc12_b memory control 16 adc12mctl16 40h adc12_b memory control 17 adc12mctl17 42h adc12_b memory control 18 adc12mctl18 44h adc12_b memory control 19 adc12mctl19 46h adc12_b memory control 20 adc12mctl20 48h adc12_b memory control 21 adc12mctl21 4ah adc12_b memory control 22 adc12mctl22 4ch
141 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated table 6-77. adc12_b registers (base address: 0800h) (continued) register description acronym offset adc12_b memory control 23 adc12mctl23 4eh adc12_b memory control 24 adc12mctl24 50h adc12_b memory control 25 adc12mctl25 52h adc12_b memory control 26 adc12mctl26 54h adc12_b memory control 27 adc12mctl27 56h adc12_b memory control 28 adc12mctl28 58h adc12_b memory control 29 adc12mctl29 5ah adc12_b memory control 30 adc12mctl30 5ch adc12_b memory control 31 adc12mctl31 5eh adc12_b memory 0 adc12mem0 60h adc12_b memory 1 adc12mem1 62h adc12_b memory 2 adc12mem2 64h adc12_b memory 3 adc12mem3 66h adc12_b memory 4 adc12mem4 68h adc12_b memory 5 adc12mem5 6ah adc12_b memory 6 adc12mem6 6ch adc12_b memory 7 adc12mem7 6eh adc12_b memory 8 adc12mem8 70h adc12_b memory 9 adc12mem9 72h adc12_b memory 10 adc12mem10 74h adc12_b memory 11 adc12mem11 76h adc12_b memory 12 adc12mem12 78h adc12_b memory 13 adc12mem13 7ah adc12_b memory 14 adc12mem14 7ch adc12_b memory 15 adc12mem15 7eh adc12_b memory 16 adc12mem16 80h adc12_b memory 17 adc12mem17 82h adc12_b memory 18 adc12mem18 84h adc12_b memory 19 adc12mem19 86h adc12_b memory 20 adc12mem20 88h adc12_b memory 21 adc12mem21 8ah adc12_b memory 22 adc12mem22 8ch adc12_b memory 23 adc12mem23 8eh adc12_b memory 24 adc12mem24 90h adc12_b memory 25 adc12mem25 92h adc12_b memory 26 adc12mem26 94h adc12_b memory 27 adc12mem27 96h adc12_b memory 28 adc12mem28 98h adc12_b memory 29 adc12mem29 9ah adc12_b memory 30 adc12mem30 9ch adc12_b memory 31 adc12mem31 9eh
142 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated table 6-78. comparator_e registers (base address: 08c0h) register description acronym offset comparator_e control 0 cectl0 00h comparator_e control 1 cectl1 02h comparator_e control 2 cectl2 04h comparator_e control 3 cectl3 06h comparator_e interrupt ceint 0ch comparator_e interrupt vector word ceiv 0eh table 6-79. crc32 registers (base address: 0980h) register description acronym offset crc32 data input crc32diw0 00h reserved 02h reserved 04h crc32 data input reverse crc32dirbw0 06h crc32 initialization and result word 0 crc32iniresw0 08h crc32 initialization and result word 1 crc32iniresw1 0ah crc32 result reverse word 1 crc32resrw1 0ch crc32 result reverse word 0 crc32resrw1 0eh crc16 data input crc16diw0 10h reserved 12h reserved 14h crc16 data input reverse crc16dirbw0 16h crc16 initialization and result word 0 crc16iniresw0 18h reserved 1ah reserved 1ch crc16 result reverse word 0 crc16resrw0 1eh reserved 20h reserved 22h reserved 24h reserved 26h reserved 28h reserved 2ah reserved 2ch reserved 2eh table 6-80. aes accelerator registers (base address: 09c0h) register description acronym offset aes accelerator control 0 aesactl0 00h reserved 02h aes accelerator status aesastat 04h aes accelerator key aesakey 06h aes accelerator data in aesadin 008h aes accelerator data out aesadout 00ah aes accelerator xored data in aesaxdin 00ch aes accelerator xored data in (no trigger) aesaxin 00eh
143 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 detailed description copyright ? 2016 ? 2017, texas instruments incorporated 6.16 identification 6.16.1 revision identification the device revision information is shown as part of the top-side marking on the device package. the device-specific errata sheet describes these markings. for links to all of the errata sheets for the devices in this data sheet, see section 8.4 . the hardware revision is also stored in the device descriptor structure in the info block section. for details on this value, see the hardware revision entry in section 6.14 . 6.16.2 device identification the device type can be identified from the top-side marking on the device package. the device-specific errata sheet describes these markings. for links to all of the errata sheets for the devices in this data sheet, see section 8.4 . a device identification value is also stored in the device descriptor structure in the info block section. for details on this value, see the device id entry in section 6.14 . 6.16.3 jtag identification programming through the jtag interface, including reading and identifying the jtag id, is described in detail in msp430 programming with the jtag interface .
144 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 applications, implementation, and layout copyright ? 2016 ? 2017, texas instruments incorporated 7 applications, implementation, and layout note information in the following applications section is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti's customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 7.1 device connection and layout fundamentals this section discusses the recommended guidelines when designing with the msp mcu. these guidelines are to make sure that the device has proper connections for powering, programming, debugging, and optimum analog performance. 7.1.1 power supply decoupling and bulk capacitors ti recommends connecting a combination of a 1- f plus a 100-nf low-esr ceramic decoupling capacitor to each avcc and dvcc pin. higher-value capacitors may be used but can impact supply rail ramp-up time. decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few millimeters). additionally, ti recommends separated grounds with a single-point connection for better noise isolation from digital to analog circuits on the board and to achieve high analog accuracy. figure 7-1. power supply decoupling 7.1.2 external oscillator depending on the device variant (see section 3 ), the device can support a low-frequency crystal (32 khz) on the lfxt pins, a high-frequency crystal on the hfxt pins, or both. external bypass capacitors for the crystal oscillator pins are required. it is also possible to apply digital clock signals to the lfxin and hfxin input pins that meet the specifications of the respective oscillator if the appropriate lfxtbypass or hfxtbypass mode is selected. in this case, the associated lfxout and hfxout pins can be used for other purposes. if they are left unused, they must be terminated according to section 4.6 . figure 7-2 shows a typical connection diagram. digital power supply decoupling 100 nf 1 f analog power supply decoupling dvcc dvss avcc avss + + 100 nf 1 f
145 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 applications, implementation, and layout copyright ? 2016 ? 2017, texas instruments incorporated figure 7-2. typical crystal connection see msp430 32-khz crystal oscillators for more information on selecting, testing, and designing a crystal oscillator with the msp mcus. 7.1.3 jtag with the proper connections, the debugger and a hardware jtag interface (such as the msp-fet or msp-fet430uif) can be used to program and debug code on the target board. in addition, the connections also support the msp-gang production programmers, thus providing an easy way to program prototype boards, if desired. figure 7-3 shows the connections between the 14-pin jtag connector and the target device required to support in-system programming and debugging for 4-wire jtag communication. figure 7-4 shows the connections for 2-wire jtag mode (spy-bi-wire). the connections for the msp-fet and msp-fet430uif interface modules and the msp-gang are identical. both can supply vcc to the target board (through pin 2). in addition, the msp-fet and msp- fet430uif interface modules and msp-gang have a vcc sense feature that, if used, requires an alternate connection (pin 4 instead of pin 2). the vcc-sense feature senses the local vcc present on the target board (that is, a battery or other local power supply) and adjusts the output signals accordingly. figure 7-3 and figure 7-4 show a jumper block that supports both scenarios of supplying vcc to the target board. if this flexibility is not required, the desired vcc connections may be hard-wired to eliminate the jumper block. pins 2 and 4 must not be connected at the same time. for additional design information regarding the jtag interface, see the msp430 hardware tools user ? s guide . c l1 c l2 lfxin or hfxin lfxout or hfxout
146 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 applications, implementation, and layout copyright ? 2016 ? 2017, texas instruments incorporated a. if a local target power supply is used, make connection j1. if power from the debug or programming adapter is used, make connection j2. b. the upper limit for c1 is 2.2 nf when using current ti tools. figure 7-3. signal connections for 4-wire jtag communication 1 35 7 9 11 13 24 6 8 10 12 14 tdo/tditdi tms tck gnd test jtag vcc tool vcc target j1 (see note a) j2 (see note a) v cc r1 47 k w av /dvcc cc rst/nmi/sbwtdio tdo/tditdi tms tck test/sbwtck av /dv ss ss msp430frxxx c1 2.2 nf (see note b) rst important to connect copyright ? 2016, texas instruments incorporated
147 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 applications, implementation, and layout copyright ? 2016 ? 2017, texas instruments incorporated a. make connection j1 if a local target power supply is used, or make connection j2 if the target is powered from the debug or programming adapter. b. the device rst/nmi/sbwtdio pin is used in 2-wire mode for bidirectional communication with the device during jtag access, and any capacitance that is attached to this signal may affect the ability to establish a connection with the device. the upper limit for c1 is 2.2 nf when using current ti tools. figure 7-4. signal connections for 2-wire jtag communication (spy-bi-wire) 7.1.4 reset the reset pin can be configured as a reset function (default) or as an nmi function in the sfrrpcr register. in reset mode, the rst/nmi pin is active low, and a pulse applied to this pin that meets the reset timing specifications generates a bor-type device reset. setting sysnmi causes the rst/nmi pin to be configured as an external nmi source. the external nmi is edge sensitive, and its edge is selectable by sysnmiies. setting the nmiie enables the interrupt of the external nmi. when an external nmi event occurs, the nmiifg is set. the rst/nmi pin can have either a pullup or pulldown that is enabled or not. sysrstup selects either pullup or pulldown, and sysrstre causes the pullup (default) or pulldown to be enabled (default) or not. if the rst/nmi pin is unused, it is required either to select and enable the internal pullup or to connect an external 47-k pullup resistor to the rst/nmi pin with a 10-nf pulldown capacitor. the pulldown capacitor should not exceed 2.2 nf when using devices with spy-bi-wire interface in spy-bi-wire mode or in 4-wire jtag mode with ti tools like fet interfaces or gang programmers. see the msp430fr58xx, msp430fr59xx, msp430fr68xx, and msp430fr69xx family user ' s guide for more information on the referenced control registers and bits. 7.1.5 unused pins for details on the connection of unused pins, see section 4.6 . 13 5 7 9 11 13 24 6 8 10 12 14 test/sbwtck msp430frxxx rst/nmi/sbwtdio tdo/tdi tck gnd jtag r1 47 k see note b vcc tool vcc target c1 2.2 nf see note b j1 (see note a) j2 (see note a) important to connect av /dvcc cc av /dv ss ss v cc copyright ? 2016, texas instruments incorporated
148 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 applications, implementation, and layout copyright ? 2016 ? 2017, texas instruments incorporated 7.1.6 general layout recommendations ? proper grounding and short traces for external crystal to reduce parasitic capacitance. see msp430 32-khz crystal oscillators for recommended layout guidelines. ? proper bypass capacitors on dvcc, avcc, and reference pins if used. ? avoid routing any high-frequency signal close to an analog signal line. for example, keep digital switching signals such as pwm or jtag signals away from the oscillator circuit. ? see circuit board layout techniques for a detailed discussion of pcb layout considerations. this document is written primarily about op amps, but the guidelines are generally applicable for all mixed- signal applications. ? proper esd level protection should be considered to protect the device from unintended high-voltage electrostatic discharge. see msp430 system-level esd considerations for guidelines. 7.1.7 do ' s and don ' ts ti recommends powering avcc and dvcc pins from the same source. at a minimum, during power up, power down, and device operation, the voltage difference between avcc and dvcc must not exceed the limits specified in absolute maximum ratings . exceeding the specified limits may cause malfunction of the device, including erroneous writes to ram and fram. 7.2 peripheral- and interface-specific design information 7.2.1 adc12_b peripheral 7.2.1.1 partial schematic figure 7-5. adc12_b grounding and noise considerations 7.2.1.2 design requirements as with any high-resolution adc, the appropriate printed-circuit-board layout and grounding techniques should be followed to eliminate ground loops, unwanted parasitic effects, and noise. ground loops are formed when return current from the adc flows through paths that are common with other analog or digital circuitry. if care is not taken, this current can generate small, unwanted offset voltages that can add to or subtract from the reference or input voltages of the adc. the general guidelines in section 7.1.1 , combined with the connections shown in section 7.2.1.1 , prevent these offsets. in addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital switching or switching power supplies can corrupt the conversion result. ti recommends a noise-free design using separate analog and digital ground planes with a single-point connection to achieve high accuracy. using an external positive reference using an external negative reference veref- vref+/veref+ + + 4.7 f 10 f 4.7 f 10 f avss
149 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 applications, implementation, and layout copyright ? 2016 ? 2017, texas instruments incorporated figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used. the internal reference module has a maximum drive current as specified in the i o(vref+) parameter of the reference module. the reference voltage must be a stable voltage for accurate measurements. the capacitor values that are selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage enters the device. in this case, the 10- f capacitor is used to buffer the reference pin and filter any low- frequency ripple. a 4.7- f bypass capacitor filters out any high-frequency noise. 7.2.1.3 detailed design procedure for additional design information, see designing with the msp430fr58xx, fr59xx, fr68xx, and fr69xx adc . 7.2.1.4 layout guidelines components that are shown in the partial schematic (see figure 7-5 ) should be placed as close as possible to the respective device pins. avoid long traces, because they add additional parasitic capacitance, inductance, and resistance on the signal. avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency pwm), because the high-frequency switching can be coupled into the analog signal. if differential mode is used for the adc12_b, the analog differential input signals must be routed closely together to minimize the effect of noise on the resulting signal.
150 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 device and documentation support copyright ? 2016 ? 2017, texas instruments incorporated 8 device and documentation support 8.1 getting started and next steps for more information on the msp family of microcontrollers and the tools and libraries that are available to help with your development, visit the getting started page . 8.2 device nomenclature to designate the stages in the product development cycle, ti assigns prefixes to the part numbers of all msp mcu devices and support tools. each msp mcu commercial family member has one of three prefixes: msp, pms, or xms (for example, msp430fr5994). ti recommends two of three possible prefix designators for its support tools: msp and mspx. these prefixes represent evolutionary stages of product development from engineering prototypes (with xms for devices and mspx for tools) through fully qualified production devices and tools (with msp for devices and msp for tools). device development evolutionary flow: xms ? experimental device that is not necessarily representative of the final device's electrical specifications msp ? fully qualified production device support tool development evolutionary flow: mspx ? development-support product that has not yet completed ti internal qualification testing. msp ? fully-qualified development-support product xms devices and mspx development-support tools are shipped against the following disclaimer: "developmental product is intended for internal evaluation purposes." msp devices and msp development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. ti's standard warranty applies. predictions show that prototype devices (xms) have a greater failure rate than the standard production devices. ti recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. only qualified production devices are to be used. ti device nomenclature also includes a suffix with the device family name. this suffix indicates the package type (for example, rgc) and temperature range (for example, t). figure 8-1 provides a legend for reading the complete device name for any family member.
151 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 device and documentation support copyright ? 2016 ? 2017, texas instruments incorporated figure 8-1. device nomenclature feature set series processor family optional: temperature range platform device type optional: distribution format packaging msp 430 fr 5 9941 i rgc t optional: bsl fram aes oscillators, lea processorfamily msp = mixed signal processor xms = experimental silicon platform 430 = tis 16-bit msp430 low-power microcontroller platform device type memory type fr = fram series fram 5 series = up to 16 mhz featureset first digit: aes 9 = aes second digit: oscillators, lea 9 = hfxt/lfxt and lea 6 = hfxt/lfxt third digit: fram (kb)4 = 256 2 = 128 optional fourth digit: bsl 1 = i c no value = uart 2 optional: temperature range packaging www.ti.com/packaging optional:distribution format optional: additional features -q1 = -ep = enhanced product (C40c to 105c) -ht = extreme temperature parts (C55c to 150c) automotive qualified t = small reel r = large reel no markings = tube or tray s = 0c to 50 c i = C40 c to 85 c t = C40 c to 105 c
152 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 device and documentation support copyright ? 2016 ? 2017, texas instruments incorporated 8.3 tools and software all msp microcontrollers are supported by a wide variety of software and hardware development tools. tools are available from ti and various third parties. see them all at development kits and software for low-power mcus . see the code composer studio for msp430 ? user ' s guide for details on the available hardware features. table 8-1 lists the debug features supported in the hardware of the msp430fr599x and msp430fr596x mcus. table 8-1. debug features msp architecture 4-wire jtag 2-wire jtag break- points (n) range break- points clock control state sequencer trace buffer lpmx.5 debugging support energytrace++ technology msp430xv2 yes yes 3 yes yes no no yes yes energytrace ? technology is supported with code composer studio version 6.0 and newer. it requires specialized debugger circuitry, which is supported with the second-generation onboard ez-fet flash emulation tool and second-generation stand-alone msp-fet jtag emulator. see the following documents for detailed information: msp430 advanced power optimizations: ulp advisor ? and energytrace ? technology advanced debugging using the enhanced emulation module (eem) with code composer studio ide msp430 hardware tools user ' s guide design kits and evaluation modules msp430fr5994 launchpad ? development kit the msp-exp430fr5994 launchpad development kit is an easy-to-use evaluation module (evm) for the msp430fr5994 microcontroller (mcu). it contains everything needed to start developing on the ultra-low-power msp430frx fram microcontroller platform, including an onboard debug probe for programming, debugging, and energy measurements. 80-pin target development board for msp430f599x mcus the msp-ts430pn80b is a stand-alone 80-pin zif socket target board that is used to program and debug the msp430 mcu in- system through the jtag interface or the spy bi-wire (2-wire jtag) protocol. software msp430ware ? software msp430ware software is a collection of code examples, data sheets, and other design resources for all msp430 devices delivered in a convenient package. in addition to providing a complete collection of existing msp430 mcu design resources, msp430ware software also includes a high-level api called msp driver library. this library makes it easy to program msp430 hardware. msp430ware software is available as a component of ccs or as a stand-alone package. msp430fr599x, msp430fr596x code examples c code examples are available for every msp device that configures each of the integrated peripherals for various application needs. capacitive touch software library free c libraries for enabling capacitive touch capabilities on msp430 mcus. the library features several capacitive touch implementations including the ro and rc method. in addition to the full c code libraries, hardware design considerations are also provided as a simple guide for including capacitive touch into any msp430 mcu- based application. msp energytrace technology energytrace technology for msp430 microcontrollers is an energy- based code analysis tool that measures and displays the application ? s energy profile and helps to optimize it for ultra-low-power consumption.
153 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 device and documentation support copyright ? 2016 ? 2017, texas instruments incorporated msp driver library driver library's abstracted api keeps you above the bits and bytes of the msp430 hardware by providing easy-to-use function calls. thorough documentation is delivered through a helpful api guide, which includes details on each function call and the recognized parameters. developers can use driver library functions to write complete projects with minimal overhead. digital signal processing library the texas instruments digital signal processing library is a set of highly optimized functions to perform many common signal processing operations on fixed- point numbers for msp430 ? and msp432 ? microcontrollers. this function set is typically used for applications where processing-intensive transforms are done in real-time for minimal energy and with very high accuracy. this library's optimal utilization of the msp families' intrinsic hardware for fixed-point math allows for significant performance gains. fram embedded software utilities for msp ultra-low-power microcontrollers the fram utilities is designed to grow as a collection of embedded software utilities that leverage the ultra-low- power and virtually unlimited write endurance of fram. the utilities are available for msp430frxx fram microcontrollers and provide example code to help start application development. included utilities include compute through power loss (ctpl). ctpl is utility api set that enables ease of use with lpmx.5 low-power modes and a powerful shutdown mode that allows an application to save and restore critical system components when a power loss is detected. development tools code composer studio integrated development environment for msp microcontrollers code composer studio is an integrated development environment (ide) that supports all msp microcontroller devices. code composer studio comprises a suite of embedded software utilities used to develop and debug embedded applications. it includes an optimizing c/c++ compiler, source code editor, project build environment, debugger, profiler, and many other features. uniflash standalone flash tool for ti microcontrollers ccs uniflash is a stand-alone tool used to program on-chip flash memory on ti mcus and on-board flash memory for sitara processors. uniflash has a gui, command line, and scripting interface. ccs uniflash is available free of charge. msp mcu programmer and debugger the msp-fet is a powerful emulation development tool ? often called a debug probe ? that allows users to quickly begin application development on msp low-power microcontrollers (mcu). creating mcu software usually requires downloading the resulting binary program to the msp device for validation and debugging. the msp-fet provides a debug communication pathway between a host computer and the target msp. msp-gang production programmer the msp gang programmer is an msp430 or msp432 device programmer that can program up to eight identical msp430 or msp432 flash or fram devices at the same time. the msp gang programmer connects to a host pc using a standard rs-232 or usb connection and provides flexible programming options that allow the user to fully customize the process. the msp gang programmer is provided with an expansion board, called the gang splitter, that implements the interconnections between the msp gang programmer and multiple target devices.
154 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 device and documentation support copyright ? 2016 ? 2017, texas instruments incorporated 8.4 documentation support the following documents describe the msp430fr599x and msp430fr596x mcus. copies of these documents are available on the internet at www.ti.com . receiving notification of document updates to receive notification of documentation updates ? including silicon errata ? go to the product folder for your device on ti.com (for links to the product folders, see section 8.5 ). in the upper right corner, click the "alert me" button. this registers you to receive a weekly digest of product information that has changed (if any). for change details, check the revision history of any revised document. errata msp430fr5994 device erratasheet describes the known exceptions to the functional specifications. msp430fr59941 device erratasheet describes the known exceptions to the functional specifications. msp430fr5992 device erratasheet describes the known exceptions to the functional specifications. msp430fr5964 device erratasheet describes the known exceptions to the functional specifications. msp430fr5962 device erratasheet describes the known exceptions to the functional specifications. user's guides msp430fr58xx, msp430fr59xx, msp430fr68xx, msp430fr69xx family user ' s guide detailed description of all modules and peripherals available in this device family. msp430 programming with the bootloader (bsl) the msp430 bootloader (bsl, formerly known as the bootstrap loader) allows users to communicate with embedded memory in the msp430 microcontroller during the prototyping phase, final production, and in service. both the programmable memory (flash memory) and the data memory (ram) can be modified as required. do not confuse the bootloader with the bootstrap loader programs found in some digital signal processors (dsps) that automatically load program code (and data) from external memory to the internal memory of the dsp. msp430 programming with the jtag interface this document describes the functions that are required to erase, program, and verify the memory module of the msp430 flash-based and fram-based microcontroller families using the jtag communication port. in addition, it describes how to program the jtag access security fuse that is available on all msp430 devices. this document describes device access using both the standard 4-wire jtag interface and the 2-wire jtag interface, which is also referred to as spy-bi-wire (sbw). msp430 hardware tools user ' s guide this manual describes the hardware of the ti msp-fet430 flash emulation tool (fet). the fet is the program development tool for the msp430 ultra- low-power microcontroller. both available interface types, the parallel port interface and the usb interface, are described. application reports msp430 32-khz crystal oscillators selection of the right crystal, correct load circuit, and proper board layout are important for a stable crystal oscillator. this application report summarizes crystal oscillator function and explains the parameters to select the correct crystal for msp430 ultra- low-power operation. in addition, hints and examples for correct board layout are given. the document also contains detailed information on the possible oscillator tests to ensure stable oscillator operation in mass production. msp430 system-level esd considerations system-level esd has become increasingly demanding with silicon technology scaling towards lower voltages and the need for designing cost- effective and ultra-low-power components. this application report addresses three different esd topics to help board designers and oems understand and design robust system-level designs: (1) component-level esd testing and system-level esd testing; (2) general design guidelines for system-level esd protection at different levels; (3) introduction to system efficient esd design (seed).
155 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 www.ti.com slase54b ? march 2016 ? revised january 2017 submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 device and documentation support copyright ? 2016 ? 2017, texas instruments incorporated 8.5 related links table 8-2 lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 8-2. related links parts product folder order now technical documents tools & software support & community msp430fr5994 click here click here click here click here click here msp430fr59941 click here click here click here click here click here msp430fr5992 click here click here click here click here click here msp430fr5964 click here click here click here click here click here msp430fr5962 click here click here click here click here click here 8.6 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? community ti's engineer-to-engineer (e2e) community . created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers. ti embedded processors wiki texas instruments embedded processors wiki . established to help developers get started with embedded processors from texas instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. 8.7 trademarks launchpad, msp430ware, msp430, code composer studio, energytrace, msp432, e2e are trademarks of texas instruments. arm, cortex are registered trademarks of arm limited. 8.8 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 8.9 export control notice recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the u.s., eu, and other export administration regulations) including software, or any controlled product restricted by other applicable national regulations, received from disclosing party under nondisclosure obligations (if any), or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by u.s. or other applicable laws, without obtaining prior authorization from u.s. department of commerce and other competent government authorities to the extent required by those laws. 8.10 glossary ti glossary this glossary lists and explains terms, acronyms, and definitions.
156 msp430fr5994 , msp430fr59941 , msp430fr5992 , msp430fr5964 , msp430fr5962 slase54b ? march 2016 ? revised january 2017 www.ti.com submit documentation feedback product folder links: msp430fr5994 msp430fr59941 msp430fr5992 msp430fr5964 msp430fr5962 mechanical, packaging, and orderable information copyright ? 2016 ? 2017, texas instruments incorporated 9 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 3-feb-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples msp430fr5962ipmr preview lqfp pm 64 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5962 msp430fr5962ipnr preview lqfp pn 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5962 msp430fr5962irgzr preview vqfn rgz 48 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5962 msp430fr5962izvwr preview nfbga zvw 87 1000 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 fr5962 msp430fr5964ipm preview lqfp pm 64 160 tbd call ti call ti -40 to 85 msp430fr5964ipmr preview lqfp pm 64 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5964 msp430fr5964ipn preview lqfp pn 80 119 tbd call ti call ti -40 to 85 MSP430FR5964IPNR preview lqfp pn 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5964 msp430fr5964irgzr preview vqfn rgz 48 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5964 msp430fr5964irgzt preview vqfn rgz 48 250 tbd call ti call ti -40 to 85 msp430fr5964izvwr preview nfbga zvw 87 1000 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 fr5964 msp430fr5992ipmr preview lqfp pm 64 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5992 msp430fr5992ipnr preview lqfp pn 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5992 msp430fr5992irgzr preview vqfn rgz 48 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5992 msp430fr5992izvwr preview nfbga zvw 87 1000 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 fr5992 msp430fr59941ipm preview lqfp pm 64 160 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr59941 msp430fr59941ipmr preview lqfp pm 64 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr59941 msp430fr59941ipn preview lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr59941
package option addendum www.ti.com 3-feb-2017 addendum-page 2 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples msp430fr59941ipnr preview lqfp pn 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr59941 msp430fr59941irgzr preview vqfn rgz 48 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr59941 msp430fr59941irgzt preview vqfn rgz 48 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr59941 msp430fr59941izvw preview nfbga zvw 87 250 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 fr59941 msp430fr59941izvwr preview nfbga zvw 87 1000 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 fr59941 msp430fr5994ipm preview lqfp pm 64 160 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5994 msp430fr5994ipmr preview lqfp pm 64 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5994 msp430fr5994ipn preview lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5994 msp430fr5994ipnr preview lqfp pn 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5994 msp430fr5994irgzr preview vqfn rgz 48 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5994 msp430fr5994irgzt preview vqfn rgz 48 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 fr5994 msp430fr5994izvw preview nfbga zvw 87 119 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 fr5994 msp430fr5994izvwr preview nfbga zvw 87 1000 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 fr5994 xms430fr5994ipnr active lqfp pn 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 x430fr5994 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device.
package option addendum www.ti.com 3-feb-2017 addendum-page 3 (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant msp430fr5962izvwr nfbga zvw 87 1000 330.0 16.4 6.3 6.3 1.5 12.0 16.0 q1 msp430fr5964izvwr nfbga zvw 87 1000 330.0 16.4 6.3 6.3 1.5 12.0 16.0 q1 msp430fr5992izvwr nfbga zvw 87 1000 330.0 16.4 6.3 6.3 1.5 12.0 16.0 q1 msp430fr59941izvwr nfbga zvw 87 1000 330.0 16.4 6.3 6.3 1.5 12.0 16.0 q1 msp430fr5994izvwr nfbga zvw 87 1000 330.0 16.4 6.3 6.3 1.5 12.0 16.0 q1 package materials information www.ti.com 3-feb-2017 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) msp430fr5962izvwr nfbga zvw 87 1000 336.6 336.6 31.8 msp430fr5964izvwr nfbga zvw 87 1000 336.6 336.6 31.8 msp430fr5992izvwr nfbga zvw 87 1000 336.6 336.6 31.8 msp430fr59941izvwr nfbga zvw 87 1000 336.6 336.6 31.8 msp430fr5994izvwr nfbga zvw 87 1000 336.6 336.6 31.8 package materials information www.ti.com 3-feb-2017 pack materials-page 2
mechanical data mtqf010a january 1995 revised december 1996 1 post office box 655303 ? dallas, texas 75265 pn (s-pqfp-g80) plastic quad flatpack 4040135 / b 11/96 0,17 0,27 0,13 nom 40 21 0,25 0,45 0,75 0,05 min seating plane gage plane 41 60 61 80 20 sq sq 1 13,80 14,20 12,20 9,50 typ 11,80 1,45 1,35 1,60 max 0,08 0,50 m 0,08 0 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026

mechanical data mtqf008a january 1995 revised december 1996 1 post office box 655303 ? dallas, texas 75265 pm (s-pqfp-g64) plastic quad flatpack 4040152 / c 11/96 32 17 0,13 nom 0,25 0,45 0,75 seating plane 0,05 min gage plane 0,27 33 16 48 1 0,17 49 64 sq sq 10,20 11,80 12,20 9,80 7,50 typ 1,60 max 1,45 1,35 0,08 0,50 m 0,08 0 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026 d. may also be thermally enhanced plastic with leads connected to the die pads.

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